From 51d191aad5601c2a0396e8547ca19e61b41777dd Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Fri, 3 Jun 2011 09:20:30 +0000 Subject: [PATCH] ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11735 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c | 43 ++++------ ArmPkg/Include/Drivers/PL310L2Cache.h | 79 +++++++++++++++++++ ArmPkg/Include/Library/L2X0CacheLib.h | 62 --------------- ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c | 7 +- .../Library/ArmVExpressLibCTA9x4/CTA9x4.c | 8 +- 5 files changed, 108 insertions(+), 91 deletions(-) create mode 100644 ArmPkg/Include/Drivers/PL310L2Cache.h delete mode 100644 ArmPkg/Include/Library/L2X0CacheLib.h diff --git a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c index ea03097ef2..b701978da5 100644 --- a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c +++ b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val) @@ -25,6 +25,10 @@ VOID L2x0CacheInit ( IN UINTN L2x0Base, + IN UINT32 L2x0TagLatencies, + IN UINT32 L2x0DataLatencies, + IN UINT32 L2x0AuxValue, + IN UINT32 L2x0AuxMask, IN BOOLEAN CacheEnabled ) { @@ -66,9 +70,9 @@ L2x0CacheInit ( Aux |= L2x0_AUXCTRL_AW_AWCACHE; // Use default Size Data = L2x0ReadReg(L2X0_AUXCTRL); - Aux |= Data & (0x7 << 17); + Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK; // Use default associativity - Aux |= Data & (0x1 << 16); + Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY; // Enabled I & D Prefetch Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH; @@ -88,29 +92,16 @@ L2x0CacheInit ( L2x0WriteReg(L2X0_PWRCTRL, PwrCtl); } - if (Revision >= 4) { - // Tag RAM Latency register - // - Use default latency - - // Data RAM Latency Control register - // - Use default latency - } else if (Revision >= 2) { - L2x0WriteReg(L230_TAG_LATENCY, - (L2_TAG_ACCESS_LATENCY << 8) - | (L2_TAG_ACCESS_LATENCY << 4) - | L2_TAG_SETUP_LATENCY - ); - - L2x0WriteReg(L230_DATA_LATENCY, - (L2_DATA_ACCESS_LATENCY << 8) - | (L2_DATA_ACCESS_LATENCY << 4) - | L2_DATA_SETUP_LATENCY - ); - } else { - Aux |= (L2_TAG_ACCESS_LATENCY << 6) - | (L2_DATA_ACCESS_LATENCY << 3) - | L2_DATA_ACCESS_LATENCY; - } + if (Revision >= 2) { + L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies); + L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies); + } else { + // PL310 old style latency is not supported yet + ASSERT(0); + } + + // Set the platform specific values + Aux = (Aux & L2x0AuxMask) | L2x0AuxValue; // Write Auxiliary value L2x0WriteReg(L2X0_AUXCTRL, Aux); diff --git a/ArmPkg/Include/Drivers/PL310L2Cache.h b/ArmPkg/Include/Drivers/PL310L2Cache.h new file mode 100644 index 0000000000..a610998062 --- /dev/null +++ b/ArmPkg/Include/Drivers/PL310L2Cache.h @@ -0,0 +1,79 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef L2CACHELIB_H_ +#define L2CACHELIB_H_ + +#define L2X0_CACHEID 0x000 +#define L2X0_CTRL 0x100 +#define L2X0_AUXCTRL 0x104 +#define L230_TAG_LATENCY 0x108 +#define L230_DATA_LATENCY 0x10C +#define L2X0_INTCLEAR 0x220 +#define L2X0_CACHE_SYNC 0x730 +#define L2X0_INVWAY 0x77C +#define L2X0_CLEAN_WAY 0x7BC +#define L2X0_PFCTRL 0xF60 +#define L2X0_PWRCTRL 0xF80 + +#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41 +#define L2X0_CACHEID_PARTNUM_PL310 0x03 + +#define L2X0_CTRL_ENABLED 0x1 +#define L2X0_CTRL_DISABLED 0x0 + +#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12) +#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16) +#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17) +#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17) +#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17) +#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17) +#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17) +#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17) +#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17) +#define L2X0_AUXCTRL_EM (1 << 20) +#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22) +#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23) +#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23) +#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23) +#define L2X0_AUXCTRL_SBO (1 << 25) +#define L2X0_AUXCTRL_NSAC (1 << 27) +#define L2x0_AUXCTRL_DPREFETCH (1 << 28) +#define L2x0_AUXCTRL_IPREFETCH (1 << 29) +#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30) + +#define L2x0_LATENCY_1_CYCLE 0 +#define L2x0_LATENCY_2_CYCLES 1 +#define L2x0_LATENCY_3_CYCLES 2 +#define L2x0_LATENCY_4_CYCLES 3 +#define L2x0_LATENCY_5_CYCLES 4 +#define L2x0_LATENCY_6_CYCLES 5 +#define L2x0_LATENCY_7_CYCLES 6 +#define L2x0_LATENCY_8_CYCLES 7 + +#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup)) +#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) +#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) + +VOID +L2x0CacheInit ( + IN UINTN L2x0Base, + IN UINT32 L2x0TagLatencies, + IN UINT32 L2x0DataLatencies, + IN UINT32 L2x0AuxValue, + IN UINT32 L2x0AuxMask, + IN BOOLEAN CacheEnabled + ); + +#endif /* L2CACHELIB_H_ */ diff --git a/ArmPkg/Include/Library/L2X0CacheLib.h b/ArmPkg/Include/Library/L2X0CacheLib.h deleted file mode 100644 index 69754e4fbb..0000000000 --- a/ArmPkg/Include/Library/L2X0CacheLib.h +++ /dev/null @@ -1,62 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef L2CACHELIB_H_ -#define L2CACHELIB_H_ - -#define L2_LATENCY 7 - -#define L2_TAG_ACCESS_LATENCY L2_LATENCY -#define L2_TAG_SETUP_LATENCY L2_LATENCY -#define L2_DATA_ACCESS_LATENCY L2_LATENCY -#define L2_DATA_SETUP_LATENCY L2_LATENCY - - -#define L2X0_CACHEID 0x000 -#define L2X0_CTRL 0x100 -#define L2X0_AUXCTRL 0x104 -#define L230_TAG_LATENCY 0x108 -#define L230_DATA_LATENCY 0x10C -#define L2X0_INTCLEAR 0x220 -#define L2X0_CACHE_SYNC 0x730 -#define L2X0_INVWAY 0x77C -#define L2X0_CLEAN_WAY 0x7BC -#define L2X0_PFCTRL 0xF60 -#define L2X0_PWRCTRL 0xF80 - -#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41 -#define L2X0_CACHEID_PARTNUM_PL310 0x03 - -#define L2X0_CTRL_ENABLED 0x1 -#define L2X0_CTRL_DISABLED 0x0 - -#define L2X0_AUXCTRL_EXCLUSIVE (1<<12) -#define L2X0_AUXCTRL_WAYSIZE_16KB (0x001 << 17) -#define L2X0_AUXCTRL_WAYSIZE_32KB (0x010 << 17) -#define L2X0_AUXCTRL_WAYSIZE_64KB (0x011 << 17) -#define L2X0_AUXCTRL_WAYSIZE_128KB (0x100 << 17) -#define L2X0_AUXCTRL_WAYSIZE_256KB (0x101 << 17) -#define L2X0_AUXCTRL_WAYSIZE_512KB (0x110 << 17) -#define L2X0_AUXCTRL_EM (1 << 20) -#define L2x0_AUXCTRL_AW_AWCACHE (0x00 << 23) -#define L2x0_AUXCTRL_AW_NOALLOC (0x01 << 23) -#define L2x0_AUXCTRL_AW_OVERRIDE (0x10 << 23) -#define L2X0_AUXCTRL_SBO (1 << 25) -#define L2X0_AUXCTRL_NSAC (1 << 27) -#define L2x0_AUXCTRL_DPREFETCH (1 << 28) -#define L2x0_AUXCTRL_IPREFETCH (1 << 29) - -VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled); - -#endif /* L2CACHELIB_H_ */ diff --git a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c index 6193cb6132..ec0a0dd464 100644 --- a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c +++ b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c @@ -12,12 +12,17 @@ * **/ -#include +#include +#include // Initialize L2X0 Cache Controller VOID L2x0CacheInit ( IN UINTN L2x0Base, + IN UINT32 L2x0TagLatencies, + IN UINT32 L2x0DataLatencies, + IN UINT32 L2x0AuxValue, + IN UINT32 L2x0AuxMask, IN BOOLEAN CacheEnabled ) { diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index 82b4ae14cb..b8d1ff0f72 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1); @@ -186,7 +186,11 @@ ArmPlatformSecInitialize ( VOID ) { // The L2x0 controller must be intialize in Secure World - L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE); + L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), + PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES), + PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES), + 0,~0, // Use default setting for the Auxiliary Control Register + FALSE); } /**