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edk2: Remove packages moved to edk2-platforms

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https://bugzilla.tianocore.org/show_bug.cgi?id=1467
https://bugzilla.tianocore.org/show_bug.cgi?id=1374
https://bugzilla.tianocore.org/show_bug.cgi?id=1793

Remove the following packages that have been imported to
edk2-platforms/master
  * Omap35xxPkg
  * BeagleBoardPkg
  * QuarkSocPkg
  * QuarkPlatformPkg
  * Vlv2DeviceRefCodePkg
  * Vlv2TbltDevicePkg
  * OptionRomPkg

Cc: Zailiang Sun <zailiang.sun@intel.com>
Cc: Yi Qian <yi.qian@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Zailiang Sun <zailiang.sun@intel.com>
Reviewed-by: Kelly Steele <kelly.steele@intel.com>
This commit is contained in:
Michael D Kinney
2019-05-09 20:42:03 -07:00
parent 96ef5a8e30
commit 5347c48016
1101 changed files with 0 additions and 259505 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
BeagleBoardPkg/BeagleBoardPkg.dec
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@@ -1,30 +0,0 @@
#/** @file
# Beagle board package.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = BeagleBoardPkg
PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[Guids.common]
gBeagleBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } }

496
BeagleBoardPkg/BeagleBoardPkg.dsc
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@@ -1,496 +0,0 @@
#/** @file
# Beagle board package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = BeagleBoardPkg
PLATFORM_GUID = 91fa6c28-33df-46ac-aee6-292d6811ea31
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/BeagleBoard
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = BeagleBoardPkg/BeagleBoardPkg.fdf
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
ArmPlatformLib|BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardLib.inf
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
!if $(TARGET) == RELEASE
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
!else
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
!endif
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
ResetSystemLib|BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
# These libraries are used by the dynamic EFI Shell commands
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
#
# Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
# in the debugger will show load and unload commands for symbols. You can cut and paste this
# into the command window to load symbols. We should be able to use a script to do this, but
# the version of RVD I have does not support scipts accessing system memory.
#
# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
RealTimeClockLib|Omap35xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
#
# Assume everything is fixed at build
#
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
TimerLib|Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
OmapLib|Omap35xxPkg/Library/OmapLib/OmapLib.inf
OmapDmaLib|Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf
DebugAgentTimerLib|Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
GdbSerialLib|Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.inf
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
# UiApp dependencies
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
MemoryInitPeiLib|BeagleBoardPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
# 1/123 faster than Stm or Vstm version
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
[LibraryClasses.common.PEI_CORE]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffLib|BeagleBoardPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
[LibraryClasses.common.DXE_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
[LibraryClasses.common.UEFI_APPLICATION]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
[LibraryClasses.common.UEFI_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffLib|BeagleBoardPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
[LibraryClasses.ARM]
#
# It is not possible to prevent the ARM compiler for generic intrinsic functions.
# This library provides the instrinsic functions generate by a given compiler.
# [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
#
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
# Add support for GCC stack protector
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
[BuildOptions]
XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
# Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Beagle Board"
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED 0x02
# DEBUG_CODE_ENABLED 0x04
# CLEAR_MEMORY_ENABLED 0x08
# ASSERT_BREAKPOINT_ENABLED 0x10
# ASSERT_DEADLOOP_ENABLED 0x20
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
!else
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
!endif
# DEBUG_INIT 0x00000001 // Initialization
# DEBUG_WARN 0x00000002 // Warnings
# DEBUG_LOAD 0x00000004 // Load events
# DEBUG_FS 0x00000008 // EFI File system
# DEBUG_POOL 0x00000010 // Alloc & Free (pool)
# DEBUG_PAGE 0x00000020 // Alloc & Free (page)
# DEBUG_INFO 0x00000040 // Informational debug messages
# DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
# DEBUG_VARIABLE 0x00000100 // Variable
# DEBUG_BM 0x00000400 // Boot Manager
# DEBUG_BLKIO 0x00001000 // BlkIo Driver
# DEBUG_NET 0x00004000 // SNP Driver
# DEBUG_UNDI 0x00010000 // UNDI Driver
# DEBUG_LOADFILE 0x00020000 // LoadFile
# DEBUG_EVENT 0x00080000 // Event messages
# DEBUG_GCD 0x00100000 // Global Coherency Database changes
# DEBUG_CACHE 0x00200000 // Memory range cachability changes
# DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
# // significantly impact boot performance
# DEBUG_ERROR 0x80000000 // Error
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
#
# Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
# Values are in EFI Pages (4K). DXE Core will make sure that
# at least this much of each type of memory can be allocated
# from a single memory range. This way you only end up with
# maximum of two fragements for each type in the memory map
# (the memory used, and the free memory that was prereserved
# but not used).
#
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
#
# Beagle board Specific PCDs
#
gArmTokenSpaceGuid.PcdVFPEnabled|1
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x08000000
# Size of the region used by UEFI in permanent memory (Reserved 16MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x01000000
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|77
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|13000000
# OMAP Interrupt Controller
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress|0x48200000
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
# GUID of the UEFI Shell
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
# GUID of the UI app
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
#
# Make VariableRuntimeDxe work at emulated non-volatile variable mode.
#
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# SEC
#
BeagleBoardPkg/PrePi/PeiUniCore.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
NULL|BeagleBoardPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf
}
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
#
# This version uses semi-hosting console
# EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf {
# <LibraryClasses>
# SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
# }
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
#
# Semi-hosting filesystem
#
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
#
# USB
#
Omap35xxPkg/PciEmulation/PciEmulation.inf
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff
}
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Nand Flash
#
Omap35xxPkg/Flash/Flash.inf
#
# MMC/SD
#
EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
Omap35xxPkg/MmcHostDxe/MmcHostDxe.inf
#
# I2C
#
Omap35xxPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
Omap35xxPkg/Gpio/Gpio.inf
Omap35xxPkg/InterruptDxe/InterruptDxe.inf
Omap35xxPkg/TimerDxe/TimerDxe.inf
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
#
# Power IC
#
Omap35xxPkg/TPS65950Dxe/TPS65950.inf
#
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
}
#
# Shell
#
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
}

308
BeagleBoardPkg/BeagleBoardPkg.fdf
View File

@@ -1,308 +0,0 @@
# FLASH layout file for Beagle board.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.BeagleBoard_EFI]
BaseAddress = 0x80007DF8|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
Size = 0x000B0000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x1
NumBlocks = 0xB0000
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
0x00000000|0x00000200
FILE = BeagleBoardPkg/ConfigurationHeader.bin
0x00000200|0x00000008
DATA = {
0xF8, 0xFD, 0x0A, 0x00, # image size: 0xB0000 - 0x208 == 0xAFDF8
0x00, 0x80, 0x00, 0x80 # entry point: 0x80008000
}
0x00000208|0x000AFDF8
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x1
NumBlocks = 0 # This FV gets compressed so make it just big enough
FvAlignment = 8 # FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = d0dd3e90-343d-4cb3-8f69-772214989282
INF MdeModulePkg/Core/Dxe/DxeMain.inf
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
!if $(TARGET) == RELEASE
#
# Semi-hosting filesystem
#
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
!endif
#
# Nand Flash
#
INF Omap35xxPkg/Flash/Flash.inf
#
# MMC/SD
#
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
INF Omap35xxPkg/MmcHostDxe/MmcHostDxe.inf
#
# I2C
#
INF Omap35xxPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
INF Omap35xxPkg/Gpio/Gpio.inf
INF Omap35xxPkg/InterruptDxe/InterruptDxe.inf
INF Omap35xxPkg/TimerDxe/TimerDxe.inf
INF Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
#
# Power IC
#
INF Omap35xxPkg/TPS65950Dxe/TPS65950.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# USB Support
#
INF Omap35xxPkg/PciEmulation/PciEmulation.inf
INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
INF ShellPkg/Application/Shell/Shell.inf
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
#
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF BeagleBoardPkg/PrePi/PeiUniCore.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
################################################################################
#
# Rules are use with the [FV] section's module INF type to define
# how an FFS file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to define the
# content of the FFS file.
#
################################################################################
############################################################################
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
############################################################################
#
#[Rule.Common.DXE_DRIVER]
# FILE DRIVER = $(NAMED_GUID) {
# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
# COMPRESS PI_STD {
# GUIDED {
# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
# UI STRING="$(MODULE_NAME)" Optional
# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
# }
# }
# }
#
############################################################################
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.UEFI_DRIVER.BINARY]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION.BINARY]
FILE APPLICATION = $(NAMED_GUID) {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}

BIN
BeagleBoardPkg/ConfigurationHeader.bin
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Binary file not shown.

41
BeagleBoardPkg/ConfigurationHeader.dat
View File

@@ -1,41 +0,0 @@
PRM_CLKSRC_CTRL=0x00000080
PRM_CLKSEL=0x00000003
CM_CLKSEL1_EMU=0x03020A50
CM_CLKSEL_CORE=0x0000030A
CM_CLKSEL_WKUP=0x00000015
CM_CLKEN_PLL_DPLL3=0x00370037
CM_AUTOIDLE_PLL_DPLL3=0x00000000
CM_CLKSEL1_PLL=0x094C0C00
CM_CLKEN_PLL_DPLL4=0x00370037
CM_AUTOIDLE_PLL_DPLL4=0x00000000
CM_CLKSEL2_PLL=0x0001B00C
CM_CLKSEL3_PLL=0x00000009
CM_CLKEN_PLL_MPU=0x00000037
CM_AUTOIDLE_PLL_MPU=0x00000000
CM_CLKSEL1_PLL_MPU=0x0011F40C
CM_CLKSEL2_PLL_MPU=0x00000001
CM_CLKSTCTRL_MPU=0x00000000
SDRC_SYSCONFIG_LSB=0x0000
SDRC_CS_CFG_LSB=0x0001
SDRC_SHARING_LSB=0x0100
SDRC_ERR_TYPE_LSB=0x0000
SDRC_DLLA_CTRL=0x0000000A
SDRC_POWER=0x00000081
MEMORY_TYPE_CS0=0x0003
SDRC_MCFG_0=0x02D04011
SDRC_MR_0_LSB=0x0032
SDRC_EMR1_0_LSB=0x0000
SDRC_EMR2_0_LSB=0x0000
SDRC_EMR3_0_LSB=0x0000
SDRC_ACTIM_CTRLA_0=0xBA9DC4C6
SDRC_ACTIM_CTRLB_0=0x00012522
SDRC_RFRCTRL_0=0x0004E201
MEMORY_TYPE_CS1=0x0003
SDRC_MCFG_1=0x02D04011
SDRC_MR_1_LSB=0x0032
SDRC_EMR1_1_LSB=0x0000
SDRC_EMR2_1_LSB=0x0000
SDRC_EMR3_1_LSB=0x0000
SDRC_ACTIM_CTRLA_1=0xBA9DC4C6
SDRC_ACTIM_CTRLB_1=0x00012522
SDRC_RFRCTRL_1=0x0004E201

15
BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc
View File

@@ -1,15 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
error = continue
unload
error = abort
setreg @CP15_CONTROL = 0x0005107E
setreg @pc=0x80008208
setreg @cpsr=0x000000D3
dis/D
readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000

17
BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh
View File

@@ -1,17 +0,0 @@
#!/bin/sh
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
IN=`/usr/bin/cygpath -u $1`
OUT=`/usr/bin/cygpath -u $2`
/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \
-e 's:\\:/:g' \
-e "s/^/load\/a\/ni\/np \"/g" \
-e "s/dll /dll\" \&/g" \
$IN | /usr/bin/sort.exe --key=3 --output=$OUT

BIN
BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf
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Binary file not shown.

61
BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc
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@@ -1,61 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
error = continue
unload
error = abort
setreg @CP15_CONTROL = 0x0005107E
setreg @cpsr=0x000000D3
; General clock settings.
setmem /32 0x48307270=0x00000080
setmem /32 0x48306D40=0x00000003
setmem /32 0x48005140=0x03020A50
;Clock configuration
setmem /32 0x48004A40=0x0000030A
setmem /32 0x48004C40=0x00000015
;DPLL3 (Core) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D40=0x094C0C00
;DPLL4 (Peripheral) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D44=0x0001B00C
setmem /32 0x48004D48=0x00000009
;DPLL1 (MPU) settings
setmem /32 0x48004904=0x00000037
setmem /32 0x48004934=0x00000000
setmem /32 0x48004940=0x0011F40C
setmem /32 0x48004944=0x00000001
setmem /32 0x48004948=0x00000000
;RAM setup.
setmem /16 0x6D000010=0x0000
setmem /16 0x6D000040=0x0001
setmem /16 0x6D000044=0x0100
setmem /16 0x6D000048=0x0000
setmem /32 0x6D000060=0x0000000A
setmem /32 0x6D000070=0x00000081
setmem /16 0x6D000040=0x0003
setmem /32 0x6D000080=0x02D04011
setmem /16 0x6D000084=0x0032
setmem /16 0x6D00008C=0x0000
setmem /32 0x6D00009C=0xBA9DC4C6
setmem /32 0x6D0000A0=0x00012522
setmem /32 0x6D0000A4=0x0004E201
setmem /16 0x6D000040=0x0003
setmem /32 0x6D0000B0=0x02D04011
setmem /16 0x6D0000B4=0x0032
setmem /16 0x6D0000BC=0x0000
setmem /32 0x6D0000C4=0xBA9DC4C6
setmem /32 0x6D0000C8=0x00012522
setmem /32 0x6D0000D4=0x0004E201

17
BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc
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@@ -1,17 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
include 'ZZZZZZ/rvi_symbols_macros.inc'
macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)
host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"
include 'ZZZZZZ/rvi_symbols.inc'
load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata
unload rvi_dummy.axf
delfile rvi_dummy.axf

188
BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc
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@@ -1,188 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
define /R int compare_guid(guid1, guid2)
unsigned char *guid1;
unsigned char *guid2;
{
return strncmp(guid1, guid2, 16);
}
.
define /R unsigned char * find_system_table(mem_start, mem_size)
unsigned char *mem_start;
unsigned long mem_size;
{
unsigned char *mem_ptr;
mem_ptr = mem_start + mem_size;
do
{
mem_ptr -= 0x400000; // 4 MB
if (strncmp(mem_ptr, "IBI SYST", 8) == 0)
{
return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase
}
} while (mem_ptr > mem_start);
return 0;
}
.
define /R unsigned char * find_debug_info_table_header(system_table)
unsigned char *system_table;
{
unsigned long configuration_table_entries;
unsigned char *configuration_table;
unsigned long index;
unsigned char debug_table_guid[16];
// Fill in the debug table's guid
debug_table_guid[ 0] = 0x77;
debug_table_guid[ 1] = 0x2E;
debug_table_guid[ 2] = 0x15;
debug_table_guid[ 3] = 0x49;
debug_table_guid[ 4] = 0xDA;
debug_table_guid[ 5] = 0x1A;
debug_table_guid[ 6] = 0x64;
debug_table_guid[ 7] = 0x47;
debug_table_guid[ 8] = 0xB7;
debug_table_guid[ 9] = 0xA2;
debug_table_guid[10] = 0x7A;
debug_table_guid[11] = 0xFE;
debug_table_guid[12] = 0xFE;
debug_table_guid[13] = 0xD9;
debug_table_guid[14] = 0x5E;
debug_table_guid[15] = 0x8B;
configuration_table_entries = *(unsigned long *)(system_table + 64);
configuration_table = *(unsigned long *)(system_table + 68);
for (index = 0; index < configuration_table_entries; index++)
{
if (compare_guid(configuration_table, debug_table_guid) == 0)
{
return *(unsigned long *)(configuration_table + 16);
}
configuration_table += 20;
}
return 0;
}
.
define /R int valid_pe_header(header)
unsigned char *header;
{
if ((header[0x00] == 'M') &&
(header[0x01] == 'Z') &&
(header[0x80] == 'P') &&
(header[0x81] == 'E'))
{
return 1;
}
return 0;
}
.
define /R unsigned long pe_headersize(header)
unsigned char *header;
{
unsigned long *size;
size = header + 0x00AC;
return *size;
}
.
define /R unsigned char *pe_filename(header)
unsigned char *header;
{
unsigned long *debugOffset;
unsigned char *stringOffset;
if (valid_pe_header(header))
{
debugOffset = header + 0x0128;
stringOffset = header + *debugOffset + 0x002C;
return stringOffset;
}
return 0;
}
.
define /R int char_is_valid(c)
unsigned char c;
{
if (c >= 32 && c < 127)
return 1;
return 0;
}
.
define /R write_symbols_file(filename, mem_start, mem_size)
unsigned char *filename;
unsigned char *mem_start;
unsigned long mem_size;
{
unsigned char *system_table;
unsigned char *debug_info_table_header;
unsigned char *debug_info_table;
unsigned long debug_info_table_size;
unsigned long index;
unsigned char *debug_image_info;
unsigned char *loaded_image_protocol;
unsigned char *image_base;
unsigned char *debug_filename;
unsigned long header_size;
int status;
system_table = find_system_table(mem_start, mem_size);
if (system_table == 0)
{
return;
}
status = fopen(88, filename, "w");
debug_info_table_header = find_debug_info_table_header(system_table);
debug_info_table = *(unsigned long *)(debug_info_table_header + 8);
debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);
for (index = 0; index < (debug_info_table_size * 4); index += 4)
{
debug_image_info = *(unsigned long *)(debug_info_table + index);
if (debug_image_info == 0)
{
break;
}
loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);
image_base = *(unsigned long *)(loaded_image_protocol + 32);
debug_filename = pe_filename(image_base);
header_size = pe_headersize(image_base);
$fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;
}
fclose(88);
}
.

112
BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc
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@@ -1,112 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
error = continue
unload
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
error = abort

205
BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm
View File

@@ -1,205 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
ENTRY &ram_start &ram_size
;If system is running then stop the execution so we can load symbols.
break
;Reset all windows
WINPAGE.RESET
;Create AREA to display the symbols we are loading.
AREA.Reset
AREA.Create SYMBOL 300. 100.
AREA.View SYMBOL
AREA.Select SYMBOL
SYS.Option BE OFF
;Added based on suggestion from Lauterbach support.
MMU.TABLEWALK ON
MMU.ON
;Load symbols.
GOSUB load_symbols &ram_start &ram_size
;Open some windows and enable semihosting.
TOOLBAR ON
STATUSBAR ON
WINPAGE.RESET
WINCLEAR
WINPOS 0.0 17.0 72. 13. 0. 0. W000
SYStem
WINPOS 0.0 0.0 110. 55. 13. 1. W001
WINTABS 10. 10. 25. 62.
Data.List
WINPAGE.SELECT P000
//Enable semihosting
System.Option.BigEndian OFF
tronchip.set swi on // ARM9/10/11 variant
// configure and open semihosting channel
winpos 50% 50% 50% 50%
term.heapinfo 0 0x20000 0x30000 0x20000
term.method armswi
term.mode string
term.gate
WINPOS 115.0 0. 70. 35. 0. 1. W002
Var.Local %HEX
WINPOS 115.10 45. 48. 9. 0. 0. W003
Register
END
find_system_table:
ENTRY &mem_start &mem_size
&mem_ptr=&mem_start+&mem_size
RPT
(
&mem_ptr=&mem_ptr-0x400000 // 4 MB
&word1=Data.LONG(D:&mem_ptr)
&word2=Data.LONG(D:&mem_ptr+0x04)
IF &word1==0x20494249
(
IF &word2==0x54535953
(
&result=Data.LONG(D:&mem_ptr+0x08)
RETURN &result
)
)
)
WHILE &mem_ptr>&mem_start
&result=0
RETURN &result
compare_guid:
ENTRY &guid
IF Data.LONG(D:&guid)==0x49152E77
(
IF Data.LONG(D:&guid+0x04)==0x47641ADA
(
IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
(
IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
(
RETURN 0
)
)
)
)
RETURN 1
find_debug_info_table_header:
ENTRY &system_table
&config_table_entries=Data.LONG(D:&system_table+0x40)
&config_table_pointer=Data.LONG(D:&system_table+0x44)
RPT &config_table_entries
(
GOSUB compare_guid &config_table_pointer
ENTRY &result
IF &result==0
(
&result=Data.LONG(D:&config_table_pointer+0x10)
RETURN &result
)
&config_table_pointer=&config_table_pointer+0x14
)
RETURN 0;
valid_pe_header:
ENTRY &header
IF Data.BYTE(D:&header+0x00)==0x4D
(
IF Data.BYTE(D:&header+0x01)==0x5A
(
IF Data.BYTE(D:&header+0x80)==0x50
(
IF Data.BYTE(D:&header+0x81)==0x45
(
RETURN 1
)
)
)
)
RETURN 0
get_file_string:
ENTRY &stringOffset
local &string
&more_string=data.string(d:&stringOffset)
if (string.len("&more_string")>=128.)
(
&string="&string"+"&more_string"
&stringOffset=&stringOffset+string.len("&more_string")
//Get remaining file string
GOSUB get_file_string &stringOffset
ENTRY &more_string
&string="&string"+"&more_string"
)
else
(
&string="&string"+"&more_string"
&more_string=""
)
RETURN &string
load_symbol_file:
ENTRY &header &load_address
GOSUB valid_pe_header &header
ENTRY &result
IF &result==1
(
&debugOffset=Data.LONG(D:&header+0x0128)
&stringOffset=&header+&debugOffset+0x002C
GOSUB get_file_string &stringOffset
ENTRY &filestring
PRINT "&filestring 0x" &load_address
TDIAG Data.load.elf &filestring &load_address /nocode /noclear
)
RETURN
pe_headersize:
ENTRY &header;
RETURN Data.LONG(D:&header+0x00AC)
load_symbols:
ENTRY &mem_start &mem_size
GOSUB find_system_table &mem_start &mem_size
ENTRY &system_table
GOSUB find_debug_info_table_header &system_table
ENTRY &debug_info_table_header
&debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
&debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
&index=0
RPT &debug_info_table_size
(
&debug_image_info=Data.LONG(D:&debug_info_table+&index)
IF &debug_image_info==0
RETURN
&loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
&image_base=Data.LONG(D:&loaded_image_protocol+0x20);
GOSUB pe_headersize &image_base
ENTRY &header_size
&image_load_address=&image_base+&header_size
GOSUB load_symbol_file &image_base &image_load_address
&index=&index+0x4
)
RETURN

182
BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm
View File

@@ -1,182 +0,0 @@
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
ENTRY &ram_start &ram_size
;If system is running then stop the execution so we can load symbols.
break
;Reset all windows
WINPAGE.RESET
AREA.Reset
AREA.Create SYMBOL 300. 100.
AREA.View SYMBOL
AREA.Select SYMBOL
SYS.Option BE OFF
; Added based on suggestion from Lauterbach support.
MMU.TABLEWALK ON
MMU.ON
GOSUB load_symbols &ram_start &ram_size
;Open some windows.
WINPOS 83.125 29.063 48. 9. 0. 0. W003
Register
WINPOS 83.25 10. 48. 9. 0. 1. W002
Var.Local
END
find_system_table:
ENTRY &mem_start &mem_size
&mem_ptr=&mem_start+&mem_size
RPT
(
&mem_ptr=&mem_ptr-0x400000 // 4 MB
&word1=Data.LONG(D:&mem_ptr)
&word2=Data.LONG(D:&mem_ptr+0x04)
IF &word1==0x20494249
(
IF &word2==0x54535953
(
&result=Data.LONG(D:&mem_ptr+0x08)
RETURN &result
)
)
)
WHILE &mem_ptr>&mem_start
&result=0
RETURN &result
compare_guid:
ENTRY &guid
IF Data.LONG(D:&guid)==0x49152E77
(
IF Data.LONG(D:&guid+0x04)==0x47641ADA
(
IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
(
IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
(
RETURN 0
)
)
)
)
RETURN 1
find_debug_info_table_header:
ENTRY &system_table
&config_table_entries=Data.LONG(D:&system_table+0x40)
&config_table_pointer=Data.LONG(D:&system_table+0x44)
RPT &config_table_entries
(
GOSUB compare_guid &config_table_pointer
ENTRY &result
IF &result==0
(
&result=Data.LONG(D:&config_table_pointer+0x10)
RETURN &result
)
&config_table_pointer=&config_table_pointer+0x14
)
RETURN 0;
valid_pe_header:
ENTRY &header
IF Data.BYTE(D:&header+0x00)==0x4D
(
IF Data.BYTE(D:&header+0x01)==0x5A
(
IF Data.BYTE(D:&header+0x80)==0x50
(
IF Data.BYTE(D:&header+0x81)==0x45
(
RETURN 1
)
)
)
)
RETURN 0
get_file_string:
ENTRY &stringOffset
local &string
&more_string=data.string(d:&stringOffset)
if (string.len("&more_string")>=128.)
(
&string="&string"+"&more_string"
&stringOffset=&stringOffset+string.len("&more_string")
//Get remaining file string
GOSUB get_file_string &stringOffset
ENTRY &more_string
&string="&string"+"&more_string"
)
else
(
&string="&string"+"&more_string"
&more_string=""
)
RETURN &string
load_symbol_file:
ENTRY &header &load_address
GOSUB valid_pe_header &header
ENTRY &result
IF &result==1
(
&debugOffset=Data.LONG(D:&header+0x0128)
&stringOffset=&header+&debugOffset+0x002C
&stringOffset=&stringOffset+11.
GOSUB get_file_string &stringOffset
ENTRY &filestring
&filestring="c:"+"&filestring"
PRINT "&filestring 0x" &load_address
Data.load.elf &filestring &load_address /nocode /noclear
)
RETURN
pe_headersize:
ENTRY &header;
RETURN Data.LONG(D:&header+0x00AC)
load_symbols:
ENTRY &mem_start &mem_size
GOSUB find_system_table &mem_start &mem_size
ENTRY &system_table
GOSUB find_debug_info_table_header &system_table
ENTRY &debug_info_table_header
&debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
&debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
&index=0
RPT &debug_info_table_size
(
&debug_image_info=Data.LONG(D:&debug_info_table+&index)
IF &debug_image_info==0
RETURN
&loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
&image_base=Data.LONG(D:&loaded_image_protocol+0x20);
GOSUB pe_headersize &image_base
ENTRY &header_size
&image_load_address=&image_base+&header_size
GOSUB load_symbol_file &image_base &image_load_address
&index=&index+0x4
)
RETURN

173
BeagleBoardPkg/Include/BeagleBoard.h
View File

@@ -1,173 +0,0 @@
/** @file
* Header defining the BeagleBoard constants (Base addresses, sizes, flags)
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __BEAGLEBOARD_PLATFORM_H__
#define __BEAGLEBOARD_PLATFORM_H__
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
// SoC registers. L3 interconnects
#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
// SoC registers. L4 interconnects
#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
#if 0
/*******************************************
// Platform Memory Map
*******************************************/
// Can be NOR, DOC, DRAM, SRAM
#define ARM_EB_REMAP_BASE 0x00000000
#define ARM_EB_REMAP_SZ 0x04000000
// Motherboard Peripheral and On-chip peripheral
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
#define ARM_EB_BOARD_PERIPH_BASE 0x10000000
//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
// SMC
#define ARM_EB_SMC_BASE 0x40000000
#define ARM_EB_SMC_SZ 0x20000000
// NOR Flash 1
#define ARM_EB_SMB_NOR_BASE 0x40000000
#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
// DOC Flash
#define ARM_EB_SMB_DOC_BASE 0x44000000
#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
// SRAM
#define ARM_EB_SMB_SRAM_BASE 0x48000000
#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
// USB, Ethernet, VRAM
#define ARM_EB_SMB_PERIPH_BASE 0x4E000000
//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
// DRAM
#define ARM_EB_DRAM_BASE 0x70000000
#define ARM_EB_DRAM_SZ 0x10000000
// Logic Tile
#define ARM_EB_LOGIC_TILE_BASE 0xC0000000
#define ARM_EB_LOGIC_TILE_SZ 0x40000000
/*******************************************
// Motherboard peripherals
*******************************************/
// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
// SP810 Controller
#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
// SYSTRCL Register
#define ARM_EB_SYSCTRL 0x10001000
// Uart0
#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
#define PL011_CONSOLE_UART_SPEED 115200
// SP804 Timer Bases
#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
// PL301 RTC
#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
// Dynamic Memory Controller Base
#define ARM_EB_DMC_BASE 0x10018000
// Static Memory Controller Base
#define ARM_EB_SMC_CTRL_BASE 0x10080000
#define PL111_CLCD_BASE 0x10020000
//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
#define PL111_CLCD_VRAM_BASE 0x78000000
#define ARM_EB_SYS_OSCCLK4 0x1000001C
/*// System Configuration Controller register Base addresses
//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000
#define ARM_EB_SYS_CFGRW0_REG 0x100E2000
#define ARM_EB_SYS_CFGRW1_REG 0x100E2004
#define ARM_EB_SYS_CFGRW2_REG 0x100E2008
#define ARM_EB_CFGRW1_REMAP_NOR0 0
#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)
#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)
#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)
// PL301 Fast AXI Base Address
#define ARM_EB_FAXI_BASE 0x100E9000
// L2x0 Cache Controller Base Address
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
// PL031 RTC - Other settings
#define PL031_PPM_ACCURACY 300000000
/*******************************************
// Interrupt Map
*******************************************/
// Timer Interrupts
#define TIMER01_INTERRUPT_NUM 34
#define TIMER23_INTERRUPT_NUM 35
/*******************************************
// EFI Memory Map in Permanent Memory (DRAM)
*******************************************/
// This region is allocated at the bottom of the DRAM. It will be used
// for fixed address allocations such as Vector Table
#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
// This region is the memory declared to PEI as permanent memory for PEI
// and DXE. EFI stacks and heaps will be declared in this region.
#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000
#endif
typedef enum {
REVISION_XM,
REVISION_UNKNOWN0,
REVISION_UNKNOWN1,
REVISION_UNKNOWN2,
REVISION_UNKNOWN3,
REVISION_C4,
REVISION_C123,
REVISION_AB,
} BEAGLEBOARD_REVISION;
#endif

115
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
View File

@@ -1,115 +0,0 @@
/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/IoLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Omap3530/Omap3530.h>
#include <BeagleBoard.h>
VOID
PadConfiguration (
BEAGLEBOARD_REVISION Revision
);
VOID
ClockInit (
VOID
);
/**
Detect board revision
@return Board revision
**/
BEAGLEBOARD_REVISION
BeagleBoardGetRevision (
VOID
)
{
UINT32 OldPinDir;
UINT32 Revision;
// Read GPIO 171, 172, 173
OldPinDir = MmioRead32 (GPIO6_BASE + GPIO_OE);
MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 | BIT12 | BIT13));
Revision = MmioRead32 (GPIO6_BASE + GPIO_DATAIN);
// Restore I/O settings
MmioWrite32 (GPIO6_BASE + GPIO_OE, OldPinDir);
return (BEAGLEBOARD_REVISION)((Revision >> 11) & 0x7);
}
/**
Return the current Boot Mode
This function returns the boot reason on the platform
**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
)
{
return BOOT_WITH_FULL_CONFIGURATION;
}
/**
Initialize controllers that must setup at the early stage
Some peripherals must be initialized in Secure World.
For example, some L2x0 requires to be initialized in Secure World
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
BEAGLEBOARD_REVISION Revision;
Revision = BeagleBoardGetRevision();
// Set up Pin muxing.
PadConfiguration (Revision);
// Set up system clocking
ClockInit ();
// Turn off the functional clock for Timer 3
MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
ArmDataSynchronizationBarrier ();
// Clear IRQs
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
return RETURN_SUCCESS;
}
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = 0;
*PpiList = NULL;
}
UINTN
ArmPlatformGetCorePosition (
IN UINTN MpId
)
{
return 1;
}

41
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S
View File

@@ -1,41 +0,0 @@
#
# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#include <AsmMacroIoLib.h>
#include <AutoGen.h>
.text
.align 2
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
GCC_ASM_IMPORT(ArmReadMpidr)
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ASM_PFX(ArmPlatformIsPrimaryCore):
// BeagleBoard has a single core. We must always return 1.
mov r0, #1
bx lr
ASM_PFX(ArmPlatformPeiBootAction):
bx lr
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
// The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is
// always the MPIDR of the calling CPU.
b ASM_PFX(ArmReadMpidr)
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

47
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.asm
View File

@@ -1,47 +0,0 @@
//
// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
#include <AsmMacroIoLib.h>
#include <Base.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformPeiBootAction
EXPORT ArmPlatformIsPrimaryCore
EXPORT ArmPlatformGetPrimaryCoreMpId
IMPORT ArmReadMpidr
AREA BeagleBoardHelper, CODE, READONLY
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ArmPlatformIsPrimaryCore FUNCTION
// BeagleBoard has a single core. We must always return 1.
mov r0, #1
bx lr
ENDFUNC
ArmPlatformPeiBootAction FUNCTION
bx lr
ENDFUNC
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ArmPlatformGetPrimaryCoreMpId FUNCTION
// The BeagleBoard is a uniprocessor platform. The MPIDR of primary core is
// always the MPIDR of the calling CPU.
b ArmReadMpidr
ENDFUNC
END

48
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardLib.inf
View File

@@ -1,48 +0,0 @@
#/* @file
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
# Copyright (c) 2016, Linaro Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardLib
FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
IoLib
ArmLib
MemoryAllocationLib
[Sources.common]
BeagleBoardHelper.asm | RVCT
BeagleBoardHelper.S | GCC
BeagleBoard.c
BeagleBoardMem.c
PadConfiguration.c
Clock.c
BeagleBoardHelper.S | GCC
BeagleBoardHelper.asm | RVCT
[FixedPcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress

74
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
View File

@@ -1,74 +0,0 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <BeagleBoard.h>
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
UINTN Index = 0;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
ASSERT(VirtualMemoryMap != NULL);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
CacheAttributes = DDR_ATTRIBUTES_CACHED;
// ReMap (Either NOR Flash or DRAM)
VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// SOC Registers. L3 interconnects
VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
// SOC Registers. L4 interconnects
VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}

63
BeagleBoardPkg/Library/BeagleBoardLib/Clock.c
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@@ -1,63 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Omap3530/Omap3530.h>
VOID
ClockInit (
VOID
)
{
//DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
// Enable PLL5 and set to 120 MHz as a reference clock.
MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
// Turn on functional & interface clocks to the USBHOST power domain
MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
| CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
// Turn on functional & interface clocks to the USBTLL block.
MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
// Turn on functional & interface clocks to MMC1 and I2C1 modules.
MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
| CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
| CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
// Turn on functional & interface clocks to various Peripherals.
MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
| CM_FCLKEN_PER_EN_GPT4_ENABLE
| CM_FCLKEN_PER_EN_GPIO2_ENABLE
| CM_FCLKEN_PER_EN_GPIO3_ENABLE
| CM_FCLKEN_PER_EN_GPIO4_ENABLE
| CM_FCLKEN_PER_EN_GPIO5_ENABLE
| CM_FCLKEN_PER_EN_GPIO6_ENABLE);
MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
| CM_ICLKEN_PER_EN_GPT3_ENABLE
| CM_ICLKEN_PER_EN_GPT4_ENABLE
| CM_ICLKEN_PER_EN_GPIO2_ENABLE
| CM_ICLKEN_PER_EN_GPIO3_ENABLE
| CM_ICLKEN_PER_EN_GPIO4_ENABLE
| CM_ICLKEN_PER_EN_GPIO5_ENABLE
| CM_ICLKEN_PER_EN_GPIO6_ENABLE);
// Turn on functional & inteface clocks to various wakeup modules.
MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
| CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
| CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
}

316
BeagleBoardPkg/Library/BeagleBoardLib/PadConfiguration.c
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@@ -1,316 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Omap3530/Omap3530.h>
#include <BeagleBoard.h>
#define NUM_PINS_SHARED 232
#define NUM_PINS_ABC 6
#define NUM_PINS_XM 12
PAD_CONFIGURATION PadConfigurationTableShared[] = {
//Pin, MuxMode, PullConfig, InputEnable
{ SDRC_D0, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D1, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D2, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D3, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D4, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D5, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D6, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D7, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D8, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D9, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D10, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D11, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D12, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D13, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D14, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D15, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D16, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D17, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D18, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D19, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D20, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D21, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D22, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D23, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D24, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D25, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D26, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D27, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D28, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D29, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D30, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_D31, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_CLK, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_DQS0, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_CKE0, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ SDRC_CKE1, MUXMODE7, PULL_DISABLED, INPUT },
{ SDRC_DQS1, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_DQS2, MUXMODE0, PULL_DISABLED, INPUT },
{ SDRC_DQS3, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_A1, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A2, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A3, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A4, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A5, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A6, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A7, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A8, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A9, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_A10, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_D0, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D1, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D2, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D3, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D4, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D5, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D6, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D7, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D8, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D9, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D10, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D11, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D12, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D13, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D14, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_D15, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NCS0, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NCS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ GPMC_NCS2, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ GPMC_NCS3, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ GPMC_NCS4, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ GPMC_NCS5, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_NCS6, MUXMODE1, PULL_DISABLED, INPUT },
{ GPMC_NCS7, MUXMODE1, PULL_UP_SELECTED, INPUT },
{ GPMC_CLK, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_NADV_ALE, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NOE, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NWE, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NBE0_CLE, MUXMODE0, PULL_DISABLED, OUTPUT },
{ GPMC_NBE1, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_NWP, MUXMODE0, PULL_DISABLED, INPUT },
{ GPMC_WAIT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ GPMC_WAIT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ GPMC_WAIT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ GPMC_WAIT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ DSS_PCLK, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_HSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_PSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_ACBIAS, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA0, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA1, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA2, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA3, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA4, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA5, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA6, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA7, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA8, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA9, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA10, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA11, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA12, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA13, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA14, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA15, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA16, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA17, MUXMODE0, PULL_DISABLED, OUTPUT },
{ CAM_HS, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ CAM_VS, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ CAM_XCLKA, MUXMODE0, PULL_DISABLED, OUTPUT },
{ CAM_PCLK, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ CAM_FLD, MUXMODE4, PULL_DISABLED, OUTPUT },
{ CAM_D0, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D1, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D2, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D3, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D4, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D5, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D6, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D7, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D8, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D9, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D10, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_D11, MUXMODE0, PULL_DISABLED, INPUT },
{ CAM_XCLKB, MUXMODE0, PULL_DISABLED, OUTPUT },
{ CAM_WEN, MUXMODE4, PULL_DISABLED, INPUT },
{ CAM_STROBE, MUXMODE0, PULL_DISABLED, OUTPUT },
{ CSI2_DX0, MUXMODE0, PULL_DISABLED, INPUT },
{ CSI2_DY0, MUXMODE0, PULL_DISABLED, INPUT },
{ CSI2_DX1, MUXMODE0, PULL_DISABLED, INPUT },
{ CSI2_DY1, MUXMODE0, PULL_DISABLED, INPUT },
{ MCBSP2_FSX, MUXMODE0, PULL_DISABLED, INPUT },
{ MCBSP2_CLKX, MUXMODE0, PULL_DISABLED, INPUT },
{ MCBSP2_DR, MUXMODE0, PULL_DISABLED, INPUT },
{ MCBSP2_DX, MUXMODE0, PULL_DISABLED, OUTPUT },
{ MMC1_CLK, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ MMC1_CMD, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT4, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT5, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT6, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC1_DAT7, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MMC2_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_CMD, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT0, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT1, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT3, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT4, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT5, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT6, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MMC2_DAT7, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MCBSP3_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP3_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP3_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP3_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ UART2_CTS, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ UART2_RTS, MUXMODE0, PULL_DISABLED, OUTPUT },
{ UART2_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
{ UART2_RX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ UART1_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
{ UART1_RTS, MUXMODE4, PULL_DISABLED, OUTPUT },
{ UART1_CTS, MUXMODE4, PULL_DISABLED, OUTPUT },
{ UART1_RX, MUXMODE0, PULL_DISABLED, INPUT },
{ MCBSP4_CLKX, MUXMODE1, PULL_DISABLED, INPUT },
{ MCBSP4_DR, MUXMODE1, PULL_DISABLED, INPUT },
{ MCBSP4_DX, MUXMODE1, PULL_DISABLED, INPUT },
{ MCBSP4_FSX, MUXMODE1, PULL_DISABLED, INPUT },
{ MCBSP1_CLKR, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP1_FSR, MUXMODE4, PULL_UP_SELECTED, OUTPUT },
{ MCBSP1_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP1_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP1_CLKS, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MCBSP1_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCBSP1_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
{ UART3_CTS_RCTX,MUXMODE0, PULL_UP_SELECTED, INPUT },
{ UART3_RTS_SD, MUXMODE0, PULL_DISABLED, OUTPUT },
{ UART3_RX_IRRX, MUXMODE0, PULL_DISABLED, INPUT },
{ UART3_TX_IRTX, MUXMODE0, PULL_DISABLED, OUTPUT },
{ HSUSB0_CLK, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_STP, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ HSUSB0_DIR, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_NXT, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA0, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA1, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA2, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA3, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA4, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA5, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA6, MUXMODE0, PULL_DISABLED, INPUT },
{ HSUSB0_DATA7, MUXMODE0, PULL_DISABLED, INPUT },
{ I2C1_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ I2C1_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ I2C2_SCL, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ I2C2_SDA, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ I2C3_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ I2C3_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ HDQ_SIO, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCSPI1_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MCSPI1_SIMO, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ MCSPI1_SOMI, MUXMODE0, PULL_DISABLED, INPUT },
{ MCSPI1_CS0, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ MCSPI1_CS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
{ MCSPI1_CS2, MUXMODE4, PULL_DISABLED, OUTPUT },
{ MCSPI1_CS3, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ MCSPI2_CLK, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ MCSPI2_SIMO, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ MCSPI2_SOMI, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ MCSPI2_CS0, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ MCSPI2_CS1, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ SYS_NIRQ, MUXMODE0, PULL_UP_SELECTED, INPUT },
{ SYS_CLKOUT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ ETK_CLK, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
{ ETK_CTL, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
{ ETK_D0, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D1, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D2, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D3, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D4, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D5, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D6, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D7, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D8, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D9, MUXMODE4, PULL_UP_SELECTED, INPUT },
{ ETK_D10, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
{ ETK_D11, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
{ ETK_D12, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D13, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D14, MUXMODE3, PULL_UP_SELECTED, INPUT },
{ ETK_D15, MUXMODE3, PULL_UP_SELECTED, INPUT }
};
PAD_CONFIGURATION PadConfigurationTableAbc[] = {
{ DSS_DATA18, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA19, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA20, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA21, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA22, MUXMODE0, PULL_DISABLED, OUTPUT },
{ DSS_DATA23, MUXMODE0, PULL_DISABLED, OUTPUT }
};
PAD_CONFIGURATION PadConfigurationTableXm[] = {
{ DSS_DATA18, MUXMODE3, PULL_DISABLED, OUTPUT },
{ DSS_DATA19, MUXMODE3, PULL_DISABLED, OUTPUT },
{ DSS_DATA20, MUXMODE3, PULL_DISABLED, OUTPUT },
{ DSS_DATA21, MUXMODE3, PULL_DISABLED, OUTPUT },
{ DSS_DATA22, MUXMODE3, PULL_DISABLED, OUTPUT },
{ DSS_DATA23, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT0, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT1, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT3, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT4, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT5, MUXMODE3, PULL_DISABLED, OUTPUT },
{ SYS_BOOT6, MUXMODE3, PULL_DISABLED, OUTPUT }
};
VOID
PadConfiguration (
BEAGLEBOARD_REVISION Revision
)
{
UINTN Index;
UINT16 PadConfiguration;
PAD_CONFIGURATION *BoardConfiguration;
UINTN NumPinsToConfigure;
for (Index = 0; Index < NUM_PINS_SHARED; Index++) {
// Set up Pad configuration for particular pin.
PadConfiguration = (PadConfigurationTableShared[Index].MuxMode << MUXMODE_OFFSET);
PadConfiguration |= (PadConfigurationTableShared[Index].PullConfig << PULL_CONFIG_OFFSET);
PadConfiguration |= (PadConfigurationTableShared[Index].InputEnable << INPUTENABLE_OFFSET);
// Configure the pin with specific Pad configuration.
MmioWrite16(PadConfigurationTableShared[Index].Pin, PadConfiguration);
}
if (Revision == REVISION_XM) {
BoardConfiguration = PadConfigurationTableXm;
NumPinsToConfigure = NUM_PINS_XM;
} else {
BoardConfiguration = PadConfigurationTableAbc;
NumPinsToConfigure = NUM_PINS_ABC;
}
for (Index = 0; Index < NumPinsToConfigure; Index++) {
//Set up Pad configuration for particular pin.
PadConfiguration = (BoardConfiguration[Index].MuxMode << MUXMODE_OFFSET);
PadConfiguration |= (BoardConfiguration[Index].PullConfig << PULL_CONFIG_OFFSET);
PadConfiguration |= (BoardConfiguration[Index].InputEnable << INPUTENABLE_OFFSET);
//Configure the pin with specific Pad configuration.
MmioWrite16(BoardConfiguration[Index].Pin, PadConfiguration);
}
}

282
BeagleBoardPkg/Library/DxeHobPeCoffLib/DxeHobPeCoff.c
View File

@@ -1,282 +0,0 @@
/** @file
PE/COFF Loader Library implementation that wraps a protocol passed up from
SEC/PEI via a HOB. This is done to save space.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Protocol/PeCoffLoader.h>
PE_COFF_LOADER_PROTOCOL *gPeCoffLoader = NULL;
/**
Retrieves information about a PE/COFF image.
Computes the PeCoffHeaderOffset, IsTeImage, ImageType, ImageAddress, ImageSize,
DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and
DebugDirectoryEntryRva fields of the ImageContext structure.
If ImageContext is NULL, then return RETURN_INVALID_PARAMETER.
If the PE/COFF image accessed through the ImageRead service in the ImageContext
structure is not a supported PE/COFF image type, then return RETURN_UNSUPPORTED.
If any errors occur while computing the fields of ImageContext,
then the error status is returned in the ImageError field of ImageContext.
If the image is a TE image, then SectionAlignment is set to 0.
The ImageRead and Handle fields of ImageContext structure must be valid prior
to invoking this service.
@param ImageContext Pointer to the image context structure that describes the PE/COFF
image that needs to be examined by this function.
@retval RETURN_SUCCESS The information on the PE/COFF image was collected.
@retval RETURN_INVALID_PARAMETER ImageContext is NULL.
@retval RETURN_UNSUPPORTED The PE/COFF image is not supported.
**/
RETURN_STATUS
EFIAPI
PeCoffLoaderGetImageInfo (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
return gPeCoffLoader->GetImageInfo (ImageContext);
}
/**
Applies relocation fixups to a PE/COFF image that was loaded with PeCoffLoaderLoadImage().
If the DestinationAddress field of ImageContext is 0, then use the ImageAddress field of
ImageContext as the relocation base address. Otherwise, use the DestinationAddress field
of ImageContext as the relocation base address. The caller must allocate the relocation
fixup log buffer and fill in the FixupData field of ImageContext prior to calling this function.
The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress,
ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders,
DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of
the ImageContext structure must be valid prior to invoking this service.
If ImageContext is NULL, then ASSERT().
Note that if the platform does not maintain coherency between the instruction cache(s) and the data
cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
prior to transferring control to a PE/COFF image that is loaded using this library.
@param ImageContext Pointer to the image context structure that describes the PE/COFF
image that is being relocated.
@retval RETURN_SUCCESS The PE/COFF image was relocated.
Extended status information is in the ImageError field of ImageContext.
@retval RETURN_LOAD_ERROR The image in not a valid PE/COFF image.
Extended status information is in the ImageError field of ImageContext.
@retval RETURN_UNSUPPORTED A relocation record type is not supported.
Extended status information is in the ImageError field of ImageContext.
**/
RETURN_STATUS
EFIAPI
PeCoffLoaderRelocateImage (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
return gPeCoffLoader->RelocateImage (ImageContext);
}
/**
Loads a PE/COFF image into memory.
Loads the PE/COFF image accessed through the ImageRead service of ImageContext into the buffer
specified by the ImageAddress and ImageSize fields of ImageContext. The caller must allocate
the load buffer and fill in the ImageAddress and ImageSize fields prior to calling this function.
The EntryPoint, FixupDataSize, CodeView, PdbPointer and HiiResourceData fields of ImageContext are computed.
The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize,
DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva
fields of the ImageContext structure must be valid prior to invoking this service.
If ImageContext is NULL, then ASSERT().
Note that if the platform does not maintain coherency between the instruction cache(s) and the data
cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
prior to transferring control to a PE/COFF image that is loaded using this library.
@param ImageContext Pointer to the image context structure that describes the PE/COFF
image that is being loaded.
@retval RETURN_SUCCESS The PE/COFF image was loaded into the buffer specified by
the ImageAddress and ImageSize fields of ImageContext.
Extended status information is in the ImageError field of ImageContext.
@retval RETURN_BUFFER_TOO_SMALL The caller did not provide a large enough buffer.
Extended status information is in the ImageError field of ImageContext.
@retval RETURN_LOAD_ERROR The PE/COFF image is an EFI Runtime image with no relocations.
Extended status information is in the ImageError field of ImageContext.
@retval RETURN_INVALID_PARAMETER The image address is invalid.
Extended status information is in the ImageError field of ImageContext.
**/
RETURN_STATUS
EFIAPI
PeCoffLoaderLoadImage (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
return gPeCoffLoader->LoadImage (ImageContext);
}
/**
Reads contents of a PE/COFF image from a buffer in system memory.
This is the default implementation of a PE_COFF_LOADER_READ_FILE function
that assumes FileHandle pointer to the beginning of a PE/COFF image.
This function reads contents of the PE/COFF image that starts at the system memory
address specified by FileHandle. The read operation copies ReadSize bytes from the
PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer.
The size of the buffer actually read is returned in ReadSize.
If FileHandle is NULL, then ASSERT().
If ReadSize is NULL, then ASSERT().
If Buffer is NULL, then ASSERT().
@param FileHandle Pointer to base of the input stream
@param FileOffset Offset into the PE/COFF image to begin the read operation.
@param ReadSize On input, the size in bytes of the requested read operation.
On output, the number of bytes actually read.
@param Buffer Output buffer that contains the data read from the PE/COFF image.
@retval RETURN_SUCCESS Data is read from FileOffset from the Handle into
the buffer.
**/
RETURN_STATUS
EFIAPI
PeCoffLoaderImageReadFromMemory (
IN VOID *FileHandle,
IN UINTN FileOffset,
IN OUT UINTN *ReadSize,
OUT VOID *Buffer
)
{
return gPeCoffLoader->ReadFromMemory (
FileHandle,
FileOffset,
ReadSize,
Buffer
);
}
/**
Reapply fixups on a fixed up PE32/PE32+ image to allow virutal calling at EFI
runtime.
This function reapplies relocation fixups to the PE/COFF image specified by ImageBase
and ImageSize so the image will execute correctly when the PE/COFF image is mapped
to the address specified by VirtualImageBase. RelocationData must be identical
to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure
after this PE/COFF image was relocated with PeCoffLoaderRelocateImage().
Note that if the platform does not maintain coherency between the instruction cache(s) and the data
cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
prior to transferring control to a PE/COFF image that is loaded using this library.
@param ImageBase Base address of a PE/COFF image that has been loaded
and relocated into system memory.
@param VirtImageBase The request virtual address that the PE/COFF image is to
be fixed up for.
@param ImageSize The size, in bytes, of the PE/COFF image.
@param RelocationData A pointer to the relocation data that was collected when the PE/COFF
image was relocated using PeCoffLoaderRelocateImage().
**/
VOID
EFIAPI
PeCoffLoaderRelocateImageForRuntime (
IN PHYSICAL_ADDRESS ImageBase,
IN PHYSICAL_ADDRESS VirtImageBase,
IN UINTN ImageSize,
IN VOID *RelocationData
)
{
return gPeCoffLoader->RelocateImageForRuntime (
ImageBase,
VirtImageBase,
ImageSize,
RelocationData
);
}
/**
Unloads a loaded PE/COFF image from memory and releases its taken resource.
Releases any environment specific resources that were allocated when the image
specified by ImageContext was loaded using PeCoffLoaderLoadImage().
For NT32 emulator, the PE/COFF image loaded by system needs to release.
For real platform, the PE/COFF image loaded by Core doesn't needs to be unloaded,
this function can simply return RETURN_SUCCESS.
If ImageContext is NULL, then ASSERT().
@param ImageContext Pointer to the image context structure that describes the PE/COFF
image to be unloaded.
@retval RETURN_SUCCESS The PE/COFF image was unloaded successfully.
**/
RETURN_STATUS
EFIAPI
PeCoffLoaderUnloadImage (
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
return gPeCoffLoader->UnloadImage (ImageContext);
}
typedef struct {
EFI_HOB_GUID_TYPE Hob;
VOID *Interface;
} PROTOCOL_HOB;
/**
The constructor function caches the pointer of DXE Services Table.
The constructor function caches the pointer of DXE Services Table.
It will ASSERT() if that operation fails.
It will ASSERT() if the pointer of DXE Services Table is NULL.
It will always return EFI_SUCCESS.
@param ImageHandle The firmware allocated handle for the EFI image.
@param SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
DxeHobPeCoffLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
PROTOCOL_HOB *Hob;
Hob = GetFirstGuidHob (&gPeCoffLoaderProtocolGuid);
if (Hob == NULL) {
return EFI_NOT_FOUND;
}
gPeCoffLoader = Hob->Interface;
return EFI_SUCCESS;
}

39
BeagleBoardPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf
View File

@@ -1,39 +0,0 @@
#/** @file
# PE/COFF Loader Library implementation that wraps a protocol passed up from
# SEC/PEI via a HOB. This is done to save space.
#
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DxeHobPeCoffLib
FILE_GUID = 671C6FD7-99FB-4EE3-B640-4B1D463BC3B5
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PeCoffLib
CONSTRUCTOR = DxeHobPeCoffLibConstructor
#
# VALID_ARCHITECTURES = IA32 X64 EBC ARM
#
[Sources.common]
DxeHobPeCoff.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
DebugLib
HobLib
[Protocols]
gPeCoffLoaderProtocolGuid

44
BeagleBoardPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.c
View File

@@ -1,44 +0,0 @@
/** @file
LZMA Decompress GUIDed Section Extraction Library.
It wraps Lzma decompress interfaces to GUIDed Section Extraction interfaces
and registers them into GUIDed handler table.
Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/HobLib.h>
#include <Library/ExtractGuidedSectionLib.h>
#include <Guid/ExtractSection.h>
#include <Guid/LzmaDecompress.h>
/**
Register LzmaDecompress and LzmaDecompressGetInfo handlers with LzmaCustomerDecompressGuid.
@retval RETURN_SUCCESS Register successfully.
@retval RETURN_OUT_OF_RESOURCES No enough memory to store this handler.
**/
EFI_STATUS
EFIAPI
LzmaDecompressLibConstructor (
)
{
EXTRACT_SECTION_HOB *Hob;
Hob = GetFirstGuidHob (&gLzmaCustomDecompressGuid);
if (Hob == NULL) {
return EFI_NOT_FOUND;
}
// Locate Guided Hob
return ExtractGuidedSectionRegisterHandlers (
&gLzmaCustomDecompressGuid,
Hob->Data.SectionGetInfo,
Hob->Data.SectionExtraction
);
}

45
BeagleBoardPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf
View File

@@ -1,45 +0,0 @@
#/** @file
# LzmaCustomDecompressLib produces LZMA custom decompression algorithm.
#
# It is based on the LZMA SDK 4.65.
# LZMA SDK 4.65 was placed in the public domain on 2009-02-03.
# It was released on the http://www.7-zip.org/sdk.html website.
#
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = LzmaDecompressLib
FILE_GUID = 35194660-7421-44ad-9636-e44885f092d1
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = NULL
CONSTRUCTOR = LzmaDecompressLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources.common]
LzmaHobCustomDecompressLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[Guids]
gLzmaCustomDecompressGuid ## PRODUCED ## GUID specifies LZMA custom decompress algorithm.
[LibraryClasses]
DebugLib
HobLib
ExtractGuidedSectionLib

192
BeagleBoardPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
View File

@@ -1,192 +0,0 @@
/** @file
*
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <PiPei.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
VOID
BuildMemoryTypeInformationHob (
VOID
);
STATIC
VOID
InitMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
)
{
VOID *TranslationTableBase;
UINTN TranslationTableSize;
RETURN_STATUS Status;
//Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
// DRAM (even at the top of DRAM as it is the first permanent memory allocation)
Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));
}
}
/*++
Routine Description:
Arguments:
FileHandle - Handle of the file being invoked.
PeiServices - Describes the list of possible PEI Services.
Returns:
Status - EFI_SUCCESS if the boot mode could be set
--*/
EFI_STATUS
EFIAPI
MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize
)
{
ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
UINT64 ResourceLength;
EFI_PEI_HOB_POINTERS NextHob;
EFI_PHYSICAL_ADDRESS FdTop;
EFI_PHYSICAL_ADDRESS SystemMemoryTop;
EFI_PHYSICAL_ADDRESS ResourceTop;
BOOLEAN Found;
// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
// Ensure PcdSystemMemorySize has been set
ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
//
// Now, the permanent memory has been installed, we can call AllocatePages()
//
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED
);
//
// Check if the resource for the main system memory has been declared
//
Found = FALSE;
NextHob.Raw = GetHobList ();
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
(PcdGet64 (PcdSystemMemoryBase) >= NextHob.ResourceDescriptor->PhysicalStart) &&
(NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <= PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize)))
{
Found = TRUE;
break;
}
NextHob.Raw = GET_NEXT_HOB (NextHob);
}
if (!Found) {
// Reserved the memory space occupied by the firmware volume
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
PcdGet64 (PcdSystemMemoryBase),
PcdGet64 (PcdSystemMemorySize)
);
}
//
// Reserved the memory space occupied by the firmware volume
//
SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);
FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFdSize);
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
// core to overwrite this area we must mark the region with the attribute non-present
if ((PcdGet64 (PcdFdBaseAddress) >= PcdGet64 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {
Found = FALSE;
// Search for System Memory Hob that contains the firmware
NextHob.Raw = GetHobList ();
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
(PcdGet64 (PcdFdBaseAddress) >= NextHob.ResourceDescriptor->PhysicalStart) &&
(FdTop <= NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
{
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
if (PcdGet64 (PcdFdBaseAddress) == NextHob.ResourceDescriptor->PhysicalStart) {
if (SystemMemoryTop == FdTop) {
NextHob.ResourceDescriptor->ResourceAttribute = ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT;
} else {
// Create the System Memory HOB for the firmware with the non-present attribute
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
PcdGet64 (PcdFdBaseAddress),
PcdGet32 (PcdFdSize));
// Top of the FD is system memory available for UEFI
NextHob.ResourceDescriptor->PhysicalStart += PcdGet32(PcdFdSize);
NextHob.ResourceDescriptor->ResourceLength -= PcdGet32(PcdFdSize);
}
} else {
// Create the System Memory HOB for the firmware with the non-present attribute
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes & ~EFI_RESOURCE_ATTRIBUTE_PRESENT,
PcdGet64 (PcdFdBaseAddress),
PcdGet32 (PcdFdSize));
// Update the HOB
NextHob.ResourceDescriptor->ResourceLength = PcdGet64 (PcdFdBaseAddress) - NextHob.ResourceDescriptor->PhysicalStart;
// If there is some memory available on the top of the FD then create a HOB
if (FdTop < NextHob.ResourceDescriptor->PhysicalStart + ResourceLength) {
// Create the System Memory HOB for the remaining region (top of the FD)
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
FdTop,
ResourceTop - FdTop);
}
}
Found = TRUE;
break;
}
NextHob.Raw = GET_NEXT_HOB (NextHob);
}
ASSERT(Found);
}
// Build Memory Allocation Hob
InitMmu (MemoryTable);
if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
// Optional feature that helps prevent EFI memory map fragmentation.
BuildMemoryTypeInformationHob ();
}
return EFI_SUCCESS;
}

58
BeagleBoardPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
View File

@@ -1,58 +0,0 @@
#/** @file
#
# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = BeagleBoardMemoryInitPeiLib
FILE_GUID = e489db0a-d847-4d67-910b-48a833f6fef5
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
[Sources]
MemoryInitPeiLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
DebugLib
HobLib
ArmMmuLib
ArmPlatformLib
[Guids]
gEfiMemoryTypeInformationGuid
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
[FixedPcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize

149
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c
View File

@@ -1,149 +0,0 @@
/** @file
Do a generic Cold Reset for OMAP3550 and BeagleBoard specific Warm reset
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/ResetSystemLib.h>
#include <Omap3530/Omap3530.h>
/**
This function causes a system-wide reset (cold reset), in which
all circuitry within the system returns to its initial state. This type of
reset is asynchronous to system operation and operates without regard to
cycle boundaries.
If this function returns, it means that the system does not support cold
reset.
**/
VOID
EFIAPI
ResetCold (
VOID
)
{
//Perform cold reset of the system.
MmioOr32 (PRM_RSTCTRL, RST_DPLL3);
while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
}
/**
This function causes a system-wide initialization (warm reset), in which all
processors are set to their initial state. Pending cycles are not corrupted.
If this function returns, it means that the system does not support warm
reset.
**/
VOID
EFIAPI
ResetWarm (
VOID
)
{
ResetCold ();
}
/**
This function causes the system to enter a power state equivalent
to the ACPI G2/S5 or G3 states.
If this function returns, it means that the system does not support shut down
reset.
**/
VOID
EFIAPI
ResetShutdown (
VOID
)
{
// not implemented
}
/**
This function causes the system to enter S3 and then wake up immediately.
If this function returns, it means that the system does not support S3
feature.
**/
VOID
EFIAPI
EnterS3WithImmediateWake (
VOID
)
{
// not implemented
}
/**
This function causes a systemwide reset. The exact type of the reset is
defined by the EFI_GUID that follows the Null-terminated Unicode string passed
into ResetData. If the platform does not recognize the EFI_GUID in ResetData
the platform must pick a supported reset type to perform.The platform may
optionally log the parameters from any non-normal reset that occurs.
@param[in] DataSize The size, in bytes, of ResetData.
@param[in] ResetData The data buffer starts with a Null-terminated string,
followed by the EFI_GUID.
**/
VOID
EFIAPI
ResetPlatformSpecific (
IN UINTN DataSize,
IN VOID *ResetData
)
{
ResetCold ();
}
/**
The ResetSystem function resets the entire platform.
@param[in] ResetType The type of reset to perform.
@param[in] ResetStatus The status code for the reset.
@param[in] DataSize The size, in bytes, of ResetData.
@param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
the data buffer starts with a Null-terminated string, optionally
followed by additional binary data. The string is a description
that the caller may use to further indicate the reason for the
system reset.
**/
VOID
EFIAPI
ResetSystem (
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
IN VOID *ResetData OPTIONAL
)
{
switch (ResetType) {
case EfiResetWarm:
ResetWarm ();
break;
case EfiResetCold:
ResetCold ();
break;
case EfiResetShutdown:
ResetShutdown ();
return;
case EfiResetPlatformSpecific:
ResetPlatformSpecific (DataSize, ResetData);
return;
default:
return;
}
}

37
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
View File

@@ -1,37 +0,0 @@
#/** @file
# Reset System lib to make it easy to port new platforms
#
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardResetSystemLib
FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib
[Sources.common]
ResetSystemLib.c
[Packages]
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[Pcd.common]
gArmTokenSpaceGuid.PcdCpuResetAddress
[LibraryClasses]
IoLib
[Pcd]
gArmTokenSpaceGuid.PcdFvBaseAddress

23
BeagleBoardPkg/PrePi/Arm/ArchPrePi.c
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@@ -1,23 +0,0 @@
/** @file
*
* Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "PrePi.h"
VOID
ArchInitialize (
VOID
)
{
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
if (FixedPcdGet32 (PcdVFPEnabled)) {
ArmEnableVFP ();
}
}

124
BeagleBoardPkg/PrePi/Arm/ModuleEntryPoint.S
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@@ -1,124 +0,0 @@
//
// Copyright (c) 2011-2015, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
#include <AsmMacroIoLib.h>
#include <Chipset/ArmV7.h>
ASM_FUNC(_ModuleEntryPoint)
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
// Get ID of this CPU in Multicore system
bl ASM_PFX(ArmReadMpidr)
// Keep a copy of the MpId register value
mov r8, r0
_SetSVCMode:
// Enter SVC mode, Disable FIQ and IRQ
mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)
msr CPSR_c, r1
// Check if we can install the stack at the top of the System Memory or if we need
// to install the stacks at the bottom of the Firmware Device (case the FD is located
// at the top of the DRAM)
_SystemMemoryEndInit:
ADRL (r1, mSystemMemoryEnd)
ldrd r2, r3, [r1]
teq r3, #0
moveq r1, r2
mvnne r1, #0
_SetupStackPosition:
// r1 = SystemMemoryTop
// Calculate Top of the Firmware Device
MOV32 (r2, FixedPcdGet32(PcdFdBaseAddress))
MOV32 (r3, FixedPcdGet32(PcdFdSize) - 1)
add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize
// UEFI Memory Size (stacks are allocated in this region)
MOV32 (r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize))
//
// Reserve the memory for the UEFI region (contain stacks on its top)
//
// Calculate how much space there is between the top of the Firmware and the Top of the System Memory
subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop
bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM
cmp r0, r4
bge _SetupStack
// Case the top of stacks is the FdBaseAddress
mov r1, r2
_SetupStack:
// r1 contains the top of the stack (and the UEFI Memory)
// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
// top of the memory space)
adds r9, r1, #1
bcs _SetupOverflowStack
_SetupAlignedStack:
mov r1, r9
b _GetBaseUefiMemory
_SetupOverflowStack:
// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
// aligned (4KB)
MOV32 (r9, ~EFI_PAGE_MASK & 0xFFFFFFFF)
and r1, r1, r9
_GetBaseUefiMemory:
// Calculate the Base of the UEFI Memory
sub r9, r1, r4
_GetStackBase:
// r1 = The top of the Mpcore Stacks
// Stack for the primary core = PrimaryCoreStack
MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
sub r10, r1, r2
// Stack for the secondary core = Number of Cores - 1
MOV32 (r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
sub r10, r10, r1
// r10 = The base of the MpCore Stacks (primary stack & secondary stacks)
mov r0, r10
mov r1, r8
//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
MOV32 (r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
bl ASM_PFX(ArmPlatformStackSet)
// Is it the Primary Core ?
mov r0, r8
bl ASM_PFX(ArmPlatformIsPrimaryCore)
cmp r0, #1
bne _PrepareArguments
_PrepareArguments:
mov r0, r8
mov r1, r9
mov r2, r10
mov r3, sp
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r4, =ASM_PFX(CEntryPoint)
// Jump to PrePiCore C code
// r0 = MpId
// r1 = UefiMemoryBase
// r2 = StacksBase
blx r4
_NeverReturn:
b _NeverReturn

142
BeagleBoardPkg/PrePi/Arm/ModuleEntryPoint.asm
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@@ -1,142 +0,0 @@
//
// Copyright (c) 2011-2015, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
#include <AutoGen.h>
#include <Chipset/ArmV7.h>
INCLUDE AsmMacroIoLib.inc
IMPORT CEntryPoint
IMPORT ArmPlatformIsPrimaryCore
IMPORT ArmReadMpidr
IMPORT ArmPlatformPeiBootAction
IMPORT ArmPlatformStackSet
IMPORT mSystemMemoryEnd
EXPORT _ModuleEntryPoint
PRESERVE8
AREA PrePiCoreEntryPoint, CODE, READONLY
StartupAddr DCD CEntryPoint
_ModuleEntryPoint
// Do early platform specific actions
bl ArmPlatformPeiBootAction
// Get ID of this CPU in Multicore system
bl ArmReadMpidr
// Keep a copy of the MpId register value
mov r8, r0
_SetSVCMode
// Enter SVC mode, Disable FIQ and IRQ
mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)
msr CPSR_c, r1
// Check if we can install the stack at the top of the System Memory or if we need
// to install the stacks at the bottom of the Firmware Device (case the FD is located
// at the top of the DRAM)
_SystemMemoryEndInit
adrll r1, mSystemMemoryEnd
ldrd r2, r3, [r1]
teq r3, #0
moveq r1, r2
mvnne r1, #0
_SetupStackPosition
// r1 = SystemMemoryTop
// Calculate Top of the Firmware Device
mov32 r2, FixedPcdGet32(PcdFdBaseAddress)
mov32 r3, FixedPcdGet32(PcdFdSize)
sub r3, r3, #1
add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize
// UEFI Memory Size (stacks are allocated in this region)
mov32 r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize)
//
// Reserve the memory for the UEFI region (contain stacks on its top)
//
// Calculate how much space there is between the top of the Firmware and the Top of the System Memory
subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop
bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM
cmp r0, r4
bge _SetupStack
// Case the top of stacks is the FdBaseAddress
mov r1, r2
_SetupStack
// r1 contains the top of the stack (and the UEFI Memory)
// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
// top of the memory space)
adds r9, r1, #1
bcs _SetupOverflowStack
_SetupAlignedStack
mov r1, r9
b _GetBaseUefiMemory
_SetupOverflowStack
// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
// aligned (4KB)
mov32 r9, EFI_PAGE_MASK
and r9, r9, r1
sub r1, r1, r9
_GetBaseUefiMemory
// Calculate the Base of the UEFI Memory
sub r9, r1, r4
_GetStackBase
// r1 = The top of the Mpcore Stacks
// Stack for the primary core = PrimaryCoreStack
mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)
sub r10, r1, r2
// Stack for the secondary core = Number of Cores - 1
mov32 r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
sub r10, r10, r1
// r10 = The base of the MpCore Stacks (primary stack & secondary stacks)
mov r0, r10
mov r1, r8
//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)
mov32 r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)
bl ArmPlatformStackSet
// Is it the Primary Core ?
mov r0, r8
bl ArmPlatformIsPrimaryCore
cmp r0, #1
bne _PrepareArguments
_PrepareArguments
mov r0, r8
mov r1, r9
mov r2, r10
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r4, StartupAddr
// Jump to PrePiCore C code
// r0 = MpId
// r1 = UefiMemoryBase
// r2 = StacksBase
blx r4
_NeverReturn
b _NeverReturn
END

97
BeagleBoardPkg/PrePi/LzmaDecompress.h
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@@ -1,97 +0,0 @@
/** @file
LZMA Decompress Library header file
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __LZMA_DECOMPRESS_H___
#define __LZMA_DECOMPRESS_H___
/**
Examines a GUIDed section and returns the size of the decoded buffer and the
size of an scratch buffer required to actually decode the data in a GUIDed section.
Examines a GUIDed section specified by InputSection.
If GUID for InputSection does not match the GUID that this handler supports,
then RETURN_UNSUPPORTED is returned.
If the required information can not be retrieved from InputSection,
then RETURN_INVALID_PARAMETER is returned.
If the GUID of InputSection does match the GUID that this handler supports,
then the size required to hold the decoded buffer is returned in OututBufferSize,
the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field
from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.
If InputSection is NULL, then ASSERT().
If OutputBufferSize is NULL, then ASSERT().
If ScratchBufferSize is NULL, then ASSERT().
If SectionAttribute is NULL, then ASSERT().
@param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
@param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required
if the buffer specified by InputSection were decoded.
@param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space
if the buffer specified by InputSection were decoded.
@param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes
field of EFI_GUID_DEFINED_SECTION in the PI Specification.
@retval RETURN_SUCCESS The information about InputSection was returned.
@retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
@retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection.
**/
RETURN_STATUS
EFIAPI
LzmaGuidedSectionGetInfo (
IN CONST VOID *InputSection,
OUT UINT32 *OutputBufferSize,
OUT UINT32 *ScratchBufferSize,
OUT UINT16 *SectionAttribute
);
/**
Decompress a LZAM compressed GUIDed section into a caller allocated output buffer.
Decodes the GUIDed section specified by InputSection.
If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.
If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.
If the GUID of InputSection does match the GUID that this handler supports, then InputSection
is decoded into the buffer specified by OutputBuffer and the authentication status of this
decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the
data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise,
the decoded data will be placed in caller allocated buffer specified by OutputBuffer.
If InputSection is NULL, then ASSERT().
If OutputBuffer is NULL, then ASSERT().
If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
If AuthenticationStatus is NULL, then ASSERT().
@param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
@param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.
@param[out] ScratchBuffer A caller allocated buffer that may be required by this function
as a scratch buffer to perform the decode operation.
@param[out] AuthenticationStatus
A pointer to the authentication status of the decoded output buffer.
See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must
never be set by this handler.
@retval RETURN_SUCCESS The buffer specified by InputSection was decoded.
@retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
@retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.
**/
RETURN_STATUS
EFIAPI
LzmaGuidedSectionExtraction (
IN CONST VOID *InputSection,
OUT VOID **OutputBuffer,
OUT VOID *ScratchBuffer, OPTIONAL
OUT UINT32 *AuthenticationStatus
);
#endif // __LZMADECOMPRESS_H__

33
BeagleBoardPkg/PrePi/MainUniCore.c
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@@ -1,33 +0,0 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "PrePi.h"
VOID
PrimaryMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
)
{
PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// We must never return
ASSERT(FALSE);
}
VOID
SecondaryMain (
IN UINTN MpId
)
{
// We must never get into this function on UniCore system
ASSERT(FALSE);
}

97
BeagleBoardPkg/PrePi/PeiUniCore.inf
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@@ -1,97 +0,0 @@
#/** @file
#
# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = BeagleBoardPrePiUniCore
FILE_GUID = 8a5dc3de-fe31-4ad9-9c93-dd73626932e7
MODULE_TYPE = SEC
VERSION_STRING = 1.0
[Sources]
PrePi.c
MainUniCore.c
[Sources.ARM]
Arm/ArchPrePi.c
Arm/ModuleEntryPoint.S | GCC
Arm/ModuleEntryPoint.asm | RVCT
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
ArmPlatformStackLib
BaseLib
DebugLib
DebugAgentLib
ExtractGuidedSectionLib
HobLib
IoLib
MemoryAllocationLib
MemoryInitPeiLib
PeCoffGetEntryPointLib
PlatformPeiLib
PrePiHobListPointerLib
PrePiLib
SerialPortLib
TimerLib
[Ppis]
gArmMpCoreInfoPpiGuid
[Guids]
gArmMpCoreInfoGuid
gEfiFirmwarePerformanceGuid
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
[FixedPcd]
gArmTokenSpaceGuid.PcdVFPEnabled
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
gArmPlatformTokenSpaceGuid.PcdCoreCount
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize

179
BeagleBoardPkg/PrePi/PrePi.c
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@@ -1,179 +0,0 @@
/** @file
*
* Copyright (c) 2011-2017, ARM Limited. All rights reserved.
* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <PiPei.h>
#include <Library/DebugAgentLib.h>
#include <Library/PrePiLib.h>
#include <Library/PrintLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/PrePiHobListPointerLib.h>
#include <Library/TimerLib.h>
#include <Library/PerformanceLib.h>
#include <Ppi/GuidedSectionExtraction.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/SecPerformance.h>
#include <Guid/LzmaDecompress.h>
#include "PrePi.h"
#include "LzmaDecompress.h"
#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))
UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +
FixedPcdGet64(PcdSystemMemorySize) - 1;
EFI_STATUS
GetPlatformPpi (
IN EFI_GUID *PpiGuid,
OUT VOID **Ppi
)
{
UINTN PpiListSize;
UINTN PpiListCount;
EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINTN Index;
PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
*Ppi = PpiList->Ppi;
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
VOID
PrePiMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
)
{
EFI_HOB_HANDOFF_INFO_TABLE* HobList;
EFI_STATUS Status;
CHAR8 Buffer[100];
UINTN CharCount;
UINTN StacksSize;
FIRMWARE_SEC_PERFORMANCE Performance;
// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
ASSERT (IS_XIP() ||
((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));
// Initialize the architecture specific bits
ArchInitialize ();
// Initialize the Serial Port
SerialPortInitialize ();
CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
// Initialize the Debug Agent for Source Level Debugging
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE);
// Declare the PI/UEFI memory region
HobList = HobConstructor (
(VOID*)UefiMemoryBase,
FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
(VOID*)UefiMemoryBase,
(VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
);
PrePeiSetHobList (HobList);
// Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
ASSERT_EFI_ERROR (Status);
StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
BuildStackHob (StacksBase, StacksSize);
//TODO: Call CpuPei as a library
BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
// Store timer value logged at the beginning of firmware image execution
Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
// Build SEC Performance Data Hob
BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
// Set the Boot Mode
SetBootMode (ArmPlatformGetBootMode ());
// Initialize Platform HOBs (CpuHob and FvHob)
Status = PlatformPeim ();
ASSERT_EFI_ERROR (Status);
// Now, the HOB List has been initialized, we can register performance information
PERF_START (NULL, "PEI", NULL, StartTimeStamp);
// SEC phase needs to run library constructors by hand.
ProcessLibraryConstructorList ();
// Build HOBs to pass up our version of stuff the DXE Core needs to save space
BuildPeCoffLoaderHob ();
BuildExtractSectionHob (
&gLzmaCustomDecompressGuid,
LzmaGuidedSectionGetInfo,
LzmaGuidedSectionExtraction
);
// Assume the FV that contains the SEC (our code) also contains a compressed FV.
Status = DecompressFirstFv ();
ASSERT_EFI_ERROR (Status);
// Load the DXE Core and transfer control to it
Status = LoadDxeCoreFromFv (NULL, 0);
ASSERT_EFI_ERROR (Status);
}
VOID
CEntryPoint (
IN UINTN MpId,
IN UINTN UefiMemoryBase,
IN UINTN StacksBase
)
{
UINT64 StartTimeStamp;
// Initialize the platform specific controllers
ArmPlatformInitialize (MpId);
if (PerformanceMeasurementEnabled ()) {
// Initialize the Timer Library to setup the Timer HW controller
TimerConstructor ();
// We cannot call yet the PerformanceLib because the HOB List has not been initialized
StartTimeStamp = GetPerformanceCounter ();
} else {
StartTimeStamp = 0;
}
// Data Cache enabled on Primary core when MMU is enabled.
ArmDisableDataCache ();
// Invalidate Data cache
ArmInvalidateDataCache ();
// Invalidate instruction cache
ArmInvalidateInstructionCache ();
// Enable Instruction Caches on all cores.
ArmEnableInstructionCache ();
PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// DXE Core should always load and never return
ASSERT (FALSE);
}

90
BeagleBoardPkg/PrePi/PrePi.h
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@@ -1,90 +0,0 @@
/** @file
*
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef _PREPI_H_
#define _PREPI_H_
#include <PiPei.h>
#include <Library/PcdLib.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/HobLib.h>
#include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h>
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
extern UINT64 mSystemMemoryEnd;
RETURN_STATUS
EFIAPI
TimerConstructor (
VOID
);
VOID
PrePiMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
);
EFI_STATUS
EFIAPI
MemoryPeim (
IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
IN UINT64 UefiMemorySize
);
EFI_STATUS
EFIAPI
PlatformPeim (
VOID
);
VOID
PrimaryMain (
IN UINTN UefiMemoryBase,
IN UINTN StacksBase,
IN UINT64 StartTimeStamp
);
VOID
SecondaryMain (
IN UINTN MpId
);
// Either implemented by PrePiLib or by MemoryInitPei
VOID
BuildMemoryTypeInformationHob (
VOID
);
EFI_STATUS
GetPlatformPpi (
IN EFI_GUID *PpiGuid,
OUT VOID **Ppi
);
// Initialize the Architecture specific controllers
VOID
ArchInitialize (
VOID
);
VOID
EFIAPI
ProcessLibraryConstructorList (
VOID
);
#endif /* _PREPI_H_ */

14
BeagleBoardPkg/Tools/GNUmakefile
View File

@@ -1,14 +0,0 @@
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
CC = gcc
CFLAGS = -g
generate_image: generate_image.c
$(CC) $(CCFLAGS) $(LDFLAGS) -o generate_image generate_image.c
clean:
rm -f generate_image generate_image.exe

402
BeagleBoardPkg/Tools/generate_image.c
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@@ -1,402 +0,0 @@
/** @file
The data structures in this code come from:
OMAP35x Applications Processor Technical Reference Manual chapter 25
OMAP34xx Multimedia Device Technical Reference Manual chapter 26.4.8.
You should use the OMAP35x manual when possible. Some things, like SectionKey,
are not defined in the OMAP35x manual and you have to use the OMAP34xx manual
to find the data.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
//TOC structure as defined by OMAP35XX TRM.
typedef struct {
unsigned int Start;
unsigned int Size;
unsigned int Reserved1;
unsigned int Reserved2;
unsigned int Reserved3;
unsigned char Filename[12];
} TOC_DATA;
//NOTE: OMAP3430 TRM has CHSETTINGS and CHRAM structures.
typedef struct {
unsigned int SectionKey;
unsigned char Valid;
unsigned char Version;
unsigned short Reserved;
unsigned int Flags;
unsigned int PRM_CLKSRC_CTRL;
unsigned int PRM_CLKSEL;
unsigned int CM_CLKSEL1_EMU;
unsigned int CM_CLKSEL_CORE;
unsigned int CM_CLKSEL_WKUP;
unsigned int CM_CLKEN_PLL_DPLL3;
unsigned int CM_AUTOIDLE_PLL_DPLL3;
unsigned int CM_CLKSEL1_PLL;
unsigned int CM_CLKEN_PLL_DPLL4;
unsigned int CM_AUTOIDLE_PLL_DPLL4;
unsigned int CM_CLKSEL2_PLL;
unsigned int CM_CLKSEL3_PLL;
unsigned int CM_CLKEN_PLL_MPU;
unsigned int CM_AUTOIDLE_PLL_MPU;
unsigned int CM_CLKSEL1_PLL_MPU;
unsigned int CM_CLKSEL2_PLL_MPU;
unsigned int CM_CLKSTCTRL_MPU;
} CHSETTINGS_DATA;
typedef struct {
unsigned int SectionKey;
unsigned char Valid;
unsigned char Reserved1;
unsigned char Reserved2;
unsigned char Reserved3;
unsigned short SDRC_SYSCONFIG_LSB;
unsigned short SDRC_CS_CFG_LSB;
unsigned short SDRC_SHARING_LSB;
unsigned short SDRC_ERR_TYPE_LSB;
unsigned int SDRC_DLLA_CTRL;
unsigned short Reserved4;
unsigned short Reserved5;
unsigned int SDRC_POWER;
unsigned short MEMORY_TYPE_CS0;
unsigned short Reserved6;
unsigned int SDRC_MCFG_0;
unsigned short SDRC_MR_0_LSB;
unsigned short SDRC_EMR1_0_LSB;
unsigned short SDRC_EMR2_0_LSB;
unsigned short SDRC_EMR3_0_LSB;
unsigned int SDRC_ACTIM_CTRLA_0;
unsigned int SDRC_ACTIM_CTRLB_0;
unsigned int SDRC_RFRCTRL_0;
unsigned short MEMORY_TYPE_CS1;
unsigned short Reserved7;
unsigned int SDRC_MCFG_1;
unsigned short SDRC_MR_1_LSB;
unsigned short SDRC_EMR1_1_LSB;
unsigned short SDRC_EMR2_1_LSB;
unsigned short SDRC_EMR3_1_LSB;
unsigned int SDRC_ACTIM_CTRLA_1;
unsigned int SDRC_ACTIM_CTRLB_1;
unsigned int SDRC_RFRCTRL_1;
unsigned int Reserved8;
unsigned short Flags;
unsigned short Reserved9;
} CHRAM_DATA;
#define CHSETTINGS_START 0xA0
#define CHSETTINGS_SIZE 0x50
#define CHRAM_START 0xF0
#define CHRAM_SIZE 0x5C
#define CLOSING_TOC_ITEM_SIZE 4
unsigned char gConfigurationHeader[512];
unsigned int gImageExecutionAddress;
char *gInputImageFile = NULL;
char *gOutputImageFile = NULL;
char *gDataFile = NULL;
static
void
PrintUsage (
void
)
{
printf("Usage..\n");
}
static
void
PopulateCHSETTINGSData (
FILE *DataFile,
CHSETTINGS_DATA *CHSETTINGSData
)
{
unsigned int Value;
CHSETTINGSData->SectionKey = 0xC0C0C0C1;
CHSETTINGSData->Valid = 0x1;
CHSETTINGSData->Version = 0x1;
CHSETTINGSData->Reserved = 0x00;
CHSETTINGSData->Flags = 0x050001FD;
//General clock settings.
fscanf(DataFile, "PRM_CLKSRC_CTRL=0x%08x\n", &Value);
CHSETTINGSData->PRM_CLKSRC_CTRL = Value;
fscanf(DataFile, "PRM_CLKSEL=0x%08x\n", &Value);
CHSETTINGSData->PRM_CLKSEL = Value;
fscanf(DataFile, "CM_CLKSEL1_EMU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_EMU = Value;
//Clock configuration
fscanf(DataFile, "CM_CLKSEL_CORE=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL_CORE = Value;
fscanf(DataFile, "CM_CLKSEL_WKUP=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL_WKUP = Value;
//DPLL3 (Core) settings
fscanf(DataFile, "CM_CLKEN_PLL_DPLL3=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_DPLL3 = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL3=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL3 = Value;
fscanf(DataFile, "CM_CLKSEL1_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_PLL = Value;
//DPLL4 (Peripheral) settings
fscanf(DataFile, "CM_CLKEN_PLL_DPLL4=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_DPLL4 = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL4=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL4 = Value;
fscanf(DataFile, "CM_CLKSEL2_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL2_PLL = Value;
fscanf(DataFile, "CM_CLKSEL3_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL3_PLL = Value;
//DPLL1 (MPU) settings
fscanf(DataFile, "CM_CLKEN_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_MPU = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSEL1_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSEL2_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL2_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSTCTRL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSTCTRL_MPU = Value;
}
static
void
PopulateCHRAMData (
FILE *DataFile,
CHRAM_DATA *CHRAMData
)
{
unsigned int Value;
CHRAMData->SectionKey = 0xC0C0C0C2;
CHRAMData->Valid = 0x1;
fscanf(DataFile, "SDRC_SYSCONFIG_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_SYSCONFIG_LSB = Value;
fscanf(DataFile, "SDRC_CS_CFG_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_CS_CFG_LSB = Value;
fscanf(DataFile, "SDRC_SHARING_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_SHARING_LSB = Value;
fscanf(DataFile, "SDRC_ERR_TYPE_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_ERR_TYPE_LSB = Value;
fscanf(DataFile, "SDRC_DLLA_CTRL=0x%08x\n", &Value);
CHRAMData->SDRC_DLLA_CTRL = Value;
fscanf(DataFile, "SDRC_POWER=0x%08x\n", &Value);
CHRAMData->SDRC_POWER = Value;
fscanf(DataFile, "MEMORY_TYPE_CS0=0x%04x\n", &Value);
CHRAMData->MEMORY_TYPE_CS0 = Value;
fscanf(DataFile, "SDRC_MCFG_0=0x%08x\n", &Value);
CHRAMData->SDRC_MCFG_0 = Value;
fscanf(DataFile, "SDRC_MR_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_MR_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR1_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR1_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR2_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR2_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR3_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR3_0_LSB = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLA_0=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLA_0 = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLB_0=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLB_0 = Value;
fscanf(DataFile, "SDRC_RFRCTRL_0=0x%08x\n", &Value);
CHRAMData->SDRC_RFRCTRL_0 = Value;
fscanf(DataFile, "MEMORY_TYPE_CS1=0x%04x\n", &Value);
CHRAMData->MEMORY_TYPE_CS1 = Value;
fscanf(DataFile, "SDRC_MCFG_1=0x%08x\n", &Value);
CHRAMData->SDRC_MCFG_1 = Value;
fscanf(DataFile, "SDRC_MR_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_MR_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR1_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR1_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR2_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR2_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR3_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR3_1_LSB = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLA_1=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLA_1 = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLB_1=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLB_1 = Value;
fscanf(DataFile, "SDRC_RFRCTRL_1=0x%08x\n", &Value);
CHRAMData->SDRC_RFRCTRL_1 = Value;
CHRAMData->Flags = 0x0003;
}
static
void
PrepareConfigurationHeader (
void
)
{
TOC_DATA Toc;
CHSETTINGS_DATA CHSETTINGSData;
CHRAM_DATA CHRAMData;
unsigned int ConfigurationHdrOffset = 0;
FILE *DataFile;
// Open data file
DataFile = fopen(gDataFile, "rb");
if (DataFile == NULL) {
fprintf(stderr, "Can't open data file %s.\n", gDataFile);
exit(1);
}
//Initialize configuration header.
memset(gConfigurationHeader, 0x00, sizeof(gConfigurationHeader));
//CHSETTINGS TOC
memset(&Toc, 0x00, sizeof(TOC_DATA));
Toc.Start = CHSETTINGS_START;
Toc.Size = CHSETTINGS_SIZE;
strcpy((char *)Toc.Filename, (const char *)"CHSETTINGS");
memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
//Populate CHSETTINGS Data
memset(&CHSETTINGSData, 0x00, sizeof(CHSETTINGS_DATA));
PopulateCHSETTINGSData(DataFile, &CHSETTINGSData);
memcpy(gConfigurationHeader + Toc.Start, &CHSETTINGSData, Toc.Size);
//Adjust ConfigurationHdrOffset to point to next TOC
ConfigurationHdrOffset += sizeof(TOC_DATA);
//CHRAM TOC
memset(&Toc, 0x00, sizeof(TOC_DATA));
Toc.Start = CHRAM_START;
Toc.Size = CHRAM_SIZE;
strcpy((char *)Toc.Filename, (const char *)"CHRAM");
memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
//Populate CHRAM Data
memset(&CHRAMData, 0x00, sizeof(CHRAM_DATA));
PopulateCHRAMData(DataFile, &CHRAMData);
memcpy(gConfigurationHeader + Toc.Start, &CHRAMData, Toc.Size);
//Adjust ConfigurationHdrOffset to point to next TOC
ConfigurationHdrOffset += sizeof(TOC_DATA);
//Closing TOC item
memset(gConfigurationHeader + ConfigurationHdrOffset, 0xFF, CLOSING_TOC_ITEM_SIZE);
ConfigurationHdrOffset += CLOSING_TOC_ITEM_SIZE;
// Close data file
fclose(DataFile);
}
static
void
ConstructImage (
void
)
{
FILE *InputFile;
FILE *OutputFile;
unsigned int InputImageFileSize;
struct stat FileStat;
char Ch;
unsigned int i;
InputFile = fopen(gInputImageFile, "rb");
if (InputFile == NULL) {
fprintf(stderr, "Can't open input file.\n");
exit(0);
}
// Get the size of the input image.
fstat(fileno(InputFile), &FileStat);
InputImageFileSize = FileStat.st_size;
OutputFile = fopen(gOutputImageFile, "wb");
if (OutputFile == NULL) {
fprintf(stderr, "Can't open output file %s.\n", gOutputImageFile);
exit(0);
}
// Write Configuration header
fwrite(gConfigurationHeader, 1, sizeof(gConfigurationHeader), OutputFile);
// Write image header (Input image size, execution address)
fwrite(&InputImageFileSize, 1, 4, OutputFile);
fwrite(&gImageExecutionAddress, 1, 4, OutputFile);
// Copy input image to the output file.
for (i = 0; i < InputImageFileSize; i++) {
fread(&Ch, 1, 1, InputFile);
fwrite(&Ch, 1, 1, OutputFile);
}
fclose(InputFile);
fclose(OutputFile);
}
int
main (
int argc,
char** argv
)
{
char Ch;
unsigned char *ptr;
int i;
int TwoArg;
if (argc == 1) {
PrintUsage ();
exit(1);
}
for (i=1; i < argc; i++) {
if (argv[i][0] == '-') {
// TwoArg TRUE -E 0x123, FALSE -E0x1234
TwoArg = (argv[i][2] != ' ');
switch (argv[i][1]) {
case 'E': /* Image execution address */
gImageExecutionAddress = strtoul (TwoArg ? argv[i+1] : &argv[i][2], (char **)&ptr, 16);
break;
case 'I': /* Input image file */
gInputImageFile = TwoArg ? argv[i+1] : &argv[i][2];
break;
case 'O': /* Output image file */
gOutputImageFile = TwoArg ? argv[i+1] : &argv[i][2];
break;
case 'D': /* Data file */
gDataFile = TwoArg ? argv[i+1] : &argv[i][2];
break;
default:
abort ();
}
}
}
//Prepare configuration header
PrepareConfigurationHeader ();
//Build image with configuration header + image header + image
ConstructImage ();
return 0;
}

16
BeagleBoardPkg/Tools/makefile
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@@ -1,16 +0,0 @@
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
all: GenerateImage replace
GenerateImage: generate_image.c
$(CC) $(CCFLAGS) $(LDFLAGS) -o GenerateImage.exe generate_image.c
replace: replace.c
$(CC) $(CCFLAGS) $(LDFLAGS) -o replace.exe replace.c
clean:
del GenerateImage.exe generate_image.obj replace.exe replace.obj

140
BeagleBoardPkg/Tools/replace.c
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@@ -1,140 +0,0 @@
//
// Quick hack to work around not having sed, or any other reasonable
// way to edit a file from a script on Windows......
//
// Copyright (c) 2010, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#define TRUE 1
#define FALSE 0
typedef struct {
char *Match;
int MatchSize;
char *Replace;
} MATCH_PAIR;
void
Usage (char *Name)
{
printf ("\n%s OldFile NewFile MatchString ReplaceString [MatchString2 ReplaceString2]*\n", Name);
printf (" OldFile - Must be arg[1] File to search for MatchStrings\n");
printf (" NewFile - Must be arg[2] File where MatchString has been replaced with ReplaceString\n");
printf (" MatchString & ReplaceString. Required arguments.\n");
printf (" More MatchString/ReplaceString pairs are supported.\n");
}
//
// argv[1] - Old File
// argv[2] - New File
// argv[3+n] - Match String
// argv[4+n] - Replace string
int
main (int argc, char **argv)
{
FILE *In, *Out;
char *Key, *Replace;
int c, i, n, Len, MaxLenKey = 0, MinLenKey = INT_MAX;
unsigned long InFileSize, InFilePos;
MATCH_PAIR *Match;
int MaxMatch;
int ReadCount;
int Found;
if (argc < 5) {
fprintf (stderr, "Need at least two files and one Match/Replacement string pair\n");
Usage (argv[0]);
return -1;
} else if ((argc % 2) == 0) {
fprintf (stderr, "Match and Replace string must come in pairs\n");
return -4;
}
In = fopen (argv[1], "r");
fseek (In, 0, SEEK_END);
InFileSize = ftell (In);
if (InFileSize == 0) {
fprintf (stderr, "Could not open %s\n", argv[1]);
return -6;
}
fseek (In, 0, SEEK_SET);
Out = fopen (argv[2], "w+");
if ((In == NULL) || (Out == NULL)) {
fprintf (stderr, "Could not open %s\n", argv[2]);
return -2;
}
MaxMatch = (argc - 2)/2;
Match = calloc (MaxMatch, sizeof (MATCH_PAIR));
if (Match == NULL) {
return -7;
}
for (n=0; n < MaxMatch; n++) {
Match[n].Match = argv[3 + n*2];
Match[n].MatchSize = strlen (argv[3 + n*2]);
Match[n].Replace = argv[3 + n*2 + 1];
if (Match[n].MatchSize > MaxLenKey) {
// Max size of match/replace string pair
MaxLenKey = Match[n].MatchSize;
}
if (Match[n].MatchSize < MinLenKey) {
MinLenKey = Match[n].MatchSize;
}
}
Key = malloc (MaxLenKey);
if (Key == NULL) {
return -5;
}
// Search for a match by reading every possition of the file
// into a buffer that is as big as the maximum search key size.
// Then we can search the keys for a match. If no match
// copy the old file character to the new file. If it is a match
// then copy the replacement string into the output file.
// This code assumes the file system is smart and caches the
// file in a buffer. So all the reads don't really hit the disk.
InFilePos = 0;
while (InFilePos < (InFileSize - MinLenKey)) {
fseek (In, InFilePos, SEEK_SET);
ReadCount = fread (Key, 1, MaxLenKey, In);
for (i = 0, Found = FALSE;i < MaxMatch; i++) {
if (ReadCount >= Match[i].MatchSize) {
if (!memcmp (Key, Match[i].Match, Match[i].MatchSize)) {
InFilePos += (Match[i].MatchSize - 1);
fputs (Match[i].Replace, Out);
Found = TRUE;
break;
}
}
}
if (!Found) {
fputc (Key[0], Out);
}
InFilePos++;
}
// We stoped searching when we got to the point that we could no longer match.
// So the last few bytes of the file are not copied in the privous loop
fseek (In, InFilePos, SEEK_SET);
while ((c = fgetc (In)) != EOF) {
fputc (c, Out);
}
fclose (In);
fclose (Out);
free (Key);
free (Match);
return 0;
}

768
Omap35xxPkg/Flash/Flash.c
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@@ -1,768 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Flash.h"
NAND_PART_INFO_TABLE gNandPartInfoTable[1] = {
{ 0x2C, 0xBA, 17, 11 }
};
NAND_FLASH_INFO *gNandFlashInfo = NULL;
UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0;
//
// Device path for SemiHosting. It contains our autogened Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} FLASH_DEVICE_PATH;
FLASH_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
};
//Actual page address = Column address + Page address + Block address.
UINTN
GetActualPageAddressInBytes (
UINTN BlockIndex,
UINTN PageIndex
)
{
//BlockAddressStart = Start of the Block address in actual NAND
//PageAddressStart = Start of the Page address in actual NAND
return ((BlockIndex << gNandFlashInfo->BlockAddressStart) + (PageIndex << gNandFlashInfo->PageAddressStart));
}
VOID
NandSendCommand (
UINT8 Command
)
{
MmioWrite16(GPMC_NAND_COMMAND_0, Command);
}
VOID
NandSendAddress (
UINT8 Address
)
{
MmioWrite16(GPMC_NAND_ADDRESS_0, Address);
}
UINT16
NandReadStatus (
VOID
)
{
//Send READ STATUS command
NandSendCommand(READ_STATUS_CMD);
//Read status.
return MmioRead16(GPMC_NAND_DATA_0);
}
VOID
NandSendAddressCycles (
UINTN Address
)
{
//Column address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Column address
NandSendAddress(Address & 0x07);
Address >>= 3;
//Page and Block address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Block address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Block address
NandSendAddress(Address & 0x01);
}
VOID
GpmcInit (
VOID
)
{
//Enable Smart-idle mode.
MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value
MmioWrite32 (GPMC_IRQSTATUS, 0x0);
MmioWrite32 (GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control.
MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access.
MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
}
EFI_STATUS
NandDetectPart (
VOID
)
{
UINT8 NandInfo = 0;
UINT8 PartInfo[5];
UINTN Index;
BOOLEAN Found = FALSE;
//Send READ ID command
NandSendCommand(READ_ID_CMD);
//Send one address cycle.
NandSendAddress(0);
//Read 5-bytes to idenfity code programmed into the NAND flash devices.
//BYTE 0 = Manufacture ID
//Byte 1 = Device ID
//Byte 2, 3, 4 = Nand part specific information (Page size, Block size etc)
for (Index = 0; Index < sizeof(PartInfo); Index++) {
PartInfo[Index] = MmioRead16(GPMC_NAND_DATA_0);
}
//Check if the ManufactureId and DeviceId are part of the currently supported nand parts.
for (Index = 0; Index < sizeof(gNandPartInfoTable)/sizeof(NAND_PART_INFO_TABLE); Index++) {
if (gNandPartInfoTable[Index].ManufactureId == PartInfo[0] && gNandPartInfoTable[Index].DeviceId == PartInfo[1]) {
gNandFlashInfo->BlockAddressStart = gNandPartInfoTable[Index].BlockAddressStart;
gNandFlashInfo->PageAddressStart = gNandPartInfoTable[Index].PageAddressStart;
Found = TRUE;
break;
}
}
if (Found == FALSE) {
DEBUG ((EFI_D_ERROR, "Nand part is not currently supported. Manufacture id: %x, Device id: %x\n", PartInfo[0], PartInfo[1]));
return EFI_NOT_FOUND;
}
//Populate NAND_FLASH_INFO based on the result of READ ID command.
gNandFlashInfo->ManufactureId = PartInfo[0];
gNandFlashInfo->DeviceId = PartInfo[1];
NandInfo = PartInfo[3];
if (PAGE_SIZE(NandInfo) == PAGE_SIZE_2K_VAL) {
gNandFlashInfo->PageSize = PAGE_SIZE_2K;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Page size.\n"));
return EFI_DEVICE_ERROR;
}
if (SPARE_AREA_SIZE(NandInfo) == SPARE_AREA_SIZE_64B_VAL) {
gNandFlashInfo->SparePageSize = SPARE_AREA_SIZE_64B;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Spare area size.\n"));
return EFI_DEVICE_ERROR;
}
if (BLOCK_SIZE(NandInfo) == BLOCK_SIZE_128K_VAL) {
gNandFlashInfo->BlockSize = BLOCK_SIZE_128K;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Block size.\n"));
return EFI_DEVICE_ERROR;
}
if (ORGANIZATION(NandInfo) == ORGANIZATION_X8) {
gNandFlashInfo->Organization = 0;
} else if (ORGANIZATION(NandInfo) == ORGANIZATION_X16) {
gNandFlashInfo->Organization = 1;
}
//Calculate total number of blocks.
gNandFlashInfo->NumPagesPerBlock = DivU64x32(gNandFlashInfo->BlockSize, gNandFlashInfo->PageSize);
return EFI_SUCCESS;
}
VOID
NandConfigureEcc (
VOID
)
{
//Define ECC size 0 and size 1 to 512 bytes
MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
}
VOID
NandEnableEcc (
VOID
)
{
//Clear all the ECC result registers and select ECC result register 1
MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0
MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
}
VOID
NandDisableEcc (
VOID
)
{
//Turn off ECC engine.
MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
}
VOID
NandCalculateEcc (
VOID
)
{
UINTN Index;
UINTN EccResultRegister;
UINTN EccResult;
//Capture 32-bit ECC result for each 512-bytes chunk.
//In our case PageSize is 2K so read ECC1-ECC4 result registers and
//generate total of 12-bytes of ECC code for the particular page.
EccResultRegister = GPMC_ECC1_RESULT;
for (Index = 0; Index < gNum512BytesChunks; Index++) {
EccResult = MmioRead32 (EccResultRegister);
//Calculate ECC code from 32-bit ECC result value.
//NOTE: Following calculation is not part of TRM. We got this information
//from Beagleboard mailing list.
gEccCode[Index * 3] = EccResult & 0xFF;
gEccCode[(Index * 3) + 1] = (EccResult >> 16) & 0xFF;
gEccCode[(Index * 3) + 2] = (((EccResult >> 20) & 0xF0) | ((EccResult >> 8) & 0x0F));
//Point to next ECC result register.
EccResultRegister += 4;
}
}
EFI_STATUS
NandReadPage (
IN UINTN BlockIndex,
IN UINTN PageIndex,
OUT VOID *Buffer,
OUT UINT8 *SpareBuffer
)
{
UINTN Address;
UINTN Index;
UINTN NumMainAreaWords = (gNandFlashInfo->PageSize/2);
UINTN NumSpareAreaWords = (gNandFlashInfo->SparePageSize/2);
UINT16 *MainAreaWordBuffer = Buffer;
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
//Send READ command
NandSendCommand(PAGE_READ_CMD);
//Send 5 Address cycles to access specific device address
NandSendAddressCycles(Address);
//Send READ CONFIRM command
NandSendCommand(PAGE_READ_CONFIRM_CMD);
//Poll till device is busy.
while (Timeout) {
if ((NandReadStatus() & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Read page timed out.\n"));
return EFI_TIMEOUT;
}
//Reissue READ command
NandSendCommand(PAGE_READ_CMD);
//Enable ECC engine.
NandEnableEcc();
//Read data into the buffer.
for (Index = 0; Index < NumMainAreaWords; Index++) {
*MainAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
}
//Read spare area into the buffer.
for (Index = 0; Index < NumSpareAreaWords; Index++) {
*SpareAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
}
//Calculate ECC.
NandCalculateEcc();
//Turn off ECC engine.
NandDisableEcc();
//Perform ECC correction.
//Need to implement..
return EFI_SUCCESS;
}
EFI_STATUS
NandWritePage (
IN UINTN BlockIndex,
IN UINTN PageIndex,
OUT VOID *Buffer,
IN UINT8 *SpareBuffer
)
{
UINTN Address;
UINT16 *MainAreaWordBuffer = Buffer;
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
UINTN Index;
UINTN NandStatus;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
//Send SERIAL DATA INPUT command
NandSendCommand(PROGRAM_PAGE_CMD);
//Send 5 Address cycles to access specific device address
NandSendAddressCycles(Address);
//Enable ECC engine.
NandEnableEcc();
//Data input from Buffer
for (Index = 0; Index < (gNandFlashInfo->PageSize/2); Index++) {
MmioWrite16(GPMC_NAND_DATA_0, *MainAreaWordBuffer++);
//After each write access, device has to wait to accept data.
//Currently we may not be programming proper timing parameters to
//the GPMC_CONFIGi_0 registers and we would need to figure that out.
//Without following delay, page programming fails.
gBS->Stall(1);
}
//Calculate ECC.
NandCalculateEcc();
//Turn off ECC engine.
NandDisableEcc();
//Prepare Spare area buffer with ECC codes.
SetMem(SpareBuffer, gNandFlashInfo->SparePageSize, 0xFF);
CopyMem(&SpareBuffer[ECC_POSITION], gEccCode, gNum512BytesChunks * 3);
//Program spare area with calculated ECC.
for (Index = 0; Index < (gNandFlashInfo->SparePageSize/2); Index++) {
MmioWrite16(GPMC_NAND_DATA_0, *SpareAreaWordBuffer++);
}
//Send PROGRAM command
NandSendCommand(PROGRAM_PAGE_CONFIRM_CMD);
//Poll till device is busy.
NandStatus = 0;
while (Timeout) {
NandStatus = NandReadStatus();
if ((NandStatus & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Program page timed out.\n"));
return EFI_TIMEOUT;
}
//Bit0 indicates Pass/Fail status
if (NandStatus & NAND_FAILURE) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
EFI_STATUS
NandEraseBlock (
IN UINTN BlockIndex
)
{
UINTN Address;
UINTN NandStatus;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, 0);
//Send ERASE SETUP command
NandSendCommand(BLOCK_ERASE_CMD);
//Send 3 address cycles to device to access Page address and Block address
Address >>= 11; //Ignore column addresses
NandSendAddress(Address & 0xff);
Address >>= 8;
NandSendAddress(Address & 0xff);
Address >>= 8;
NandSendAddress(Address & 0xff);
//Send ERASE CONFIRM command
NandSendCommand(BLOCK_ERASE_CONFIRM_CMD);
//Poll till device is busy.
NandStatus = 0;
while (Timeout) {
NandStatus = NandReadStatus();
if ((NandStatus & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
gBS->Stall(1);
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Erase block timed out for Block: %d.\n", BlockIndex));
return EFI_TIMEOUT;
}
//Bit0 indicates Pass/Fail status
if (NandStatus & NAND_FAILURE) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
EFI_STATUS
NandReadBlock (
IN UINTN StartBlockIndex,
IN UINTN EndBlockIndex,
OUT VOID *Buffer,
OUT VOID *SpareBuffer
)
{
UINTN BlockIndex;
UINTN PageIndex;
EFI_STATUS Status = EFI_SUCCESS;
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
//For each block read number of pages
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
Status = NandReadPage(BlockIndex, PageIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
return Status;
}
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
}
}
return Status;
}
EFI_STATUS
NandWriteBlock (
IN UINTN StartBlockIndex,
IN UINTN EndBlockIndex,
OUT VOID *Buffer,
OUT VOID *SpareBuffer
)
{
UINTN BlockIndex;
UINTN PageIndex;
EFI_STATUS Status = EFI_SUCCESS;
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
//Page programming.
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
Status = NandWritePage(BlockIndex, PageIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
return Status;
}
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
}
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashReset (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
)
{
UINTN BusyStall = 50; // microSeconds
UINTN ResetBusyTimeout = (1000000 / BusyStall); // 1 Second
//Send RESET command to device.
NandSendCommand(RESET_CMD);
//Wait for 1ms before we check status register.
gBS->Stall(1000);
//Check BIT#5 & BIT#6 in Status register to make sure RESET is done.
while ((NandReadStatus() & NAND_RESET_STATUS) != NAND_RESET_STATUS) {
//In case of extended verification, wait for extended amount of time
//to make sure device is reset.
if (ExtendedVerification) {
if (ResetBusyTimeout == 0) {
return EFI_DEVICE_ERROR;
}
gBS->Stall(BusyStall);
ResetBusyTimeout--;
}
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
NandFlashReadBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
OUT VOID *Buffer
)
{
UINTN NumBlocks;
UINTN EndBlockIndex;
EFI_STATUS Status;
UINT8 *SpareBuffer = NULL;
if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if (Lba > LAST_BLOCK) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
Status = EFI_BAD_BUFFER_SIZE;
goto exit;
}
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
if (SpareBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
//Read block
Status = NandReadBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Read block fails: %x\n", Status));
goto exit;
}
exit:
if (SpareBuffer != NULL) {
FreePool (SpareBuffer);
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashWriteBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
IN VOID *Buffer
)
{
UINTN BlockIndex;
UINTN NumBlocks;
UINTN EndBlockIndex;
EFI_STATUS Status;
UINT8 *SpareBuffer = NULL;
if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if (Lba > LAST_BLOCK) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
Status = EFI_BAD_BUFFER_SIZE;
goto exit;
}
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
if (SpareBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
// Erase block
for (BlockIndex = (UINTN)Lba; BlockIndex <= EndBlockIndex; BlockIndex++) {
Status = NandEraseBlock(BlockIndex);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Erase block failed. Status: %x\n", Status));
goto exit;
}
}
// Program data
Status = NandWriteBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Block write fails: %x\n", Status));
goto exit;
}
exit:
if (SpareBuffer != NULL) {
FreePool (SpareBuffer);
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashFlushBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
}
EFI_BLOCK_IO_MEDIA gNandFlashMedia = {
SIGNATURE_32('n','a','n','d'), // MediaId
FALSE, // RemovableMedia
TRUE, // MediaPresent
FALSE, // LogicalPartition
FALSE, // ReadOnly
FALSE, // WriteCaching
0, // BlockSize
2, // IoAlign
0, // Pad
0 // LastBlock
};
EFI_BLOCK_IO_PROTOCOL BlockIo =
{
EFI_BLOCK_IO_INTERFACE_REVISION, // Revision
&gNandFlashMedia, // *Media
NandFlashReset, // Reset
NandFlashReadBlocks, // ReadBlocks
NandFlashWriteBlocks, // WriteBlocks
NandFlashFlushBlocks // FlushBlocks
};
EFI_STATUS
NandFlashInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
gNandFlashInfo = (NAND_FLASH_INFO *)AllocateZeroPool (sizeof(NAND_FLASH_INFO));
//Initialize GPMC module.
GpmcInit();
//Reset NAND part
NandFlashReset(&BlockIo, FALSE);
//Detect NAND part and populate gNandFlashInfo structure
Status = NandDetectPart ();
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Nand part id detection failure: Status: %x\n", Status));
return Status;
}
//Count total number of 512Bytes chunk based on the page size.
if (gNandFlashInfo->PageSize == PAGE_SIZE_512B) {
gNum512BytesChunks = 1;
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_2K) {
gNum512BytesChunks = 4;
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_4K) {
gNum512BytesChunks = 8;
}
gEccCode = (UINT8 *)AllocatePool(gNum512BytesChunks * 3);
if (gEccCode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//Configure ECC
NandConfigureEcc ();
//Patch EFI_BLOCK_IO_MEDIA structure.
gNandFlashMedia.BlockSize = gNandFlashInfo->BlockSize;
gNandFlashMedia.LastBlock = LAST_BLOCK;
//Publish BlockIO.
Status = gBS->InstallMultipleProtocolInterfaces (
&ImageHandle,
&gEfiBlockIoProtocolGuid, &BlockIo,
&gEfiDevicePathProtocolGuid, &gDevicePath,
NULL
);
return Status;
}

100
Omap35xxPkg/Flash/Flash.h
View File

@@ -1,100 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef FLASH_H
#define FLASH_H
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/IoLib.h>
#include <Protocol/BlockIo.h>
#include <Protocol/Cpu.h>
#include <Omap3530/Omap3530.h>
#define PAGE_SIZE(x) ((x) & 0x01)
#define PAGE_SIZE_2K_VAL (0x01UL)
#define SPARE_AREA_SIZE(x) (((x) >> 2) & 0x01)
#define SPARE_AREA_SIZE_64B_VAL (0x1UL)
#define BLOCK_SIZE(x) (((x) >> 4) & 0x01)
#define BLOCK_SIZE_128K_VAL (0x01UL)
#define ORGANIZATION(x) (((x) >> 6) & 0x01)
#define ORGANIZATION_X8 (0x0UL)
#define ORGANIZATION_X16 (0x1UL)
#define PAGE_SIZE_512B (512)
#define PAGE_SIZE_2K (2048)
#define PAGE_SIZE_4K (4096)
#define SPARE_AREA_SIZE_16B (16)
#define SPARE_AREA_SIZE_64B (64)
#define BLOCK_SIZE_16K (16*1024)
#define BLOCK_SIZE_128K (128*1024)
#define BLOCK_COUNT (2048)
#define LAST_BLOCK (BLOCK_COUNT - 1)
#define ECC_POSITION 2
//List of commands.
#define RESET_CMD 0xFF
#define READ_ID_CMD 0x90
#define READ_STATUS_CMD 0x70
#define PAGE_READ_CMD 0x00
#define PAGE_READ_CONFIRM_CMD 0x30
#define BLOCK_ERASE_CMD 0x60
#define BLOCK_ERASE_CONFIRM_CMD 0xD0
#define PROGRAM_PAGE_CMD 0x80
#define PROGRAM_PAGE_CONFIRM_CMD 0x10
//Nand status register bit definition
#define NAND_SUCCESS (0x0UL << 0)
#define NAND_FAILURE BIT0
#define NAND_BUSY (0x0UL << 6)
#define NAND_READY BIT6
#define NAND_RESET_STATUS (0x60UL << 0)
#define MAX_RETRY_COUNT 1500
typedef struct {
UINT8 ManufactureId;
UINT8 DeviceId;
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
UINT8 PageAddressStart; //Start of the Page address in actual NAND
} NAND_PART_INFO_TABLE;
typedef struct {
UINT8 ManufactureId;
UINT8 DeviceId;
UINT8 Organization; //x8 or x16
UINT32 PageSize;
UINT32 SparePageSize;
UINT32 BlockSize;
UINT32 NumPagesPerBlock;
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
UINT8 PageAddressStart; //Start of the Page address in actual NAND
} NAND_FLASH_INFO;
#endif //FLASH_H

42
Omap35xxPkg/Flash/Flash.inf
View File

@@ -1,42 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = NandFlash
FILE_GUID = 4d00ef14-c4e0-426b-81b7-30a00a14aad6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = NandFlashInitialize
[Sources.common]
Flash.c
[Packages]
MdePkg/MdePkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
[Guids]
[Protocols]
gEfiBlockIoProtocolGuid
gEfiCpuArchProtocolGuid
[Pcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset
[depex]
TRUE

129
Omap35xxPkg/Gpio/Gpio.c
View File

@@ -1,129 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedGpio.h>
#include <Omap3530/Omap3530.h>
EFI_STATUS
Get (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *Value
)
{
UINTN Port;
UINTN Pin;
UINT32 DataInRegister;
if (Value == NULL)
{
return EFI_UNSUPPORTED;
}
Port = GPIO_PORT(Gpio);
Pin = GPIO_PIN(Gpio);
DataInRegister = GpioBase(Port) + GPIO_DATAIN;
if (MmioRead32 (DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
*Value = 1;
} else {
*Value = 0;
}
return EFI_SUCCESS;
}
EFI_STATUS
Set (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
IN EMBEDDED_GPIO_MODE Mode
)
{
UINTN Port;
UINTN Pin;
UINT32 OutputEnableRegister;
UINT32 SetDataOutRegister;
UINT32 ClearDataOutRegister;
Port = GPIO_PORT(Gpio);
Pin = GPIO_PIN(Gpio);
OutputEnableRegister = GpioBase(Port) + GPIO_OE;
SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT;
ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT;
switch (Mode)
{
case GPIO_MODE_INPUT:
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
break;
case GPIO_MODE_OUTPUT_0:
MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
case GPIO_MODE_OUTPUT_1:
MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
default:
return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
}
EFI_STATUS
GetMode (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT EMBEDDED_GPIO_MODE *Mode
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
SetPull (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
IN EMBEDDED_GPIO_PULL Direction
)
{
return EFI_UNSUPPORTED;
}
EMBEDDED_GPIO Gpio = {
Get,
Set,
GetMode,
SetPull
};
EFI_STATUS
GpioInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL);
return Status;
}

39
Omap35xxPkg/Gpio/Gpio.inf
View File

@@ -1,39 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Gpio
FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = GpioInitialize
[Sources.common]
Gpio.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
IoLib
UefiDriverEntryPoint
OmapLib
[Guids]
[Protocols]
gEmbeddedGpioProtocolGuid
[Pcd]
[depex]
TRUE

84
Omap35xxPkg/Include/Library/OmapDmaLib.h
View File

@@ -1,84 +0,0 @@
/** @file
Abstractions for simple OMAP DMA.
OMAP_DMA4 structure elements are described in the OMAP35xx TRM.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP_DMA_LIB_H__
#define __OMAP_DMA_LIB_H__
// Example from DMA chapter of the OMAP35xx spec
typedef struct {
UINT8 DataType; // DMA4_CSDPi[1:0]
UINT8 ReadPortAccessType; // DMA4_CSDPi[8:7]
UINT8 WritePortAccessType; // DMA4_CSDPi[15:14]
UINT8 SourceEndiansim; // DMA4_CSDPi[21]
UINT8 DestinationEndianism; // DMA4_CSDPi[19]
UINT8 WriteMode; // DMA4_CSDPi[17:16]
UINT8 SourcePacked; // DMA4_CSDPi[6]
UINT8 DestinationPacked; // DMA4_CSDPi[13]
UINT32 NumberOfElementPerFrame; // DMA4_CENi
UINT32 NumberOfFramePerTransferBlock; // DMA4_CFNi
UINT32 SourceStartAddress; // DMA4_CSSAi
UINT32 DestinationStartAddress; // DMA4_CDSAi
UINT32 SourceElementIndex; // DMA4_CSEi
UINT32 SourceFrameIndex; // DMA4_CSFi
UINT32 DestinationElementIndex; // DMA4_CDEi
UINT32 DestinationFrameIndex; // DMA4_CDFi
UINT8 ReadPortAccessMode; // DMA4_CCRi[13:12]
UINT8 WritePortAccessMode; // DMA4_CCRi[15:14]
UINT8 ReadPriority; // DMA4_CCRi[6]
UINT8 WritePriority; // DMA4_CCRi[23]
UINT8 ReadRequestNumber; // DMA4_CCRi[4:0]
UINT8 WriteRequestNumber; // DMA4_CCRi[20:19]
} OMAP_DMA4;
/**
Configure OMAP DMA Channel
@param Channel DMA Channel to configure
@param Dma4 Pointer to structure used to initialize DMA registers for the Channel
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
EnableDmaChannel (
IN UINTN Channel,
IN OMAP_DMA4 *Dma4
);
/**
Turn of DMA channel configured by EnableDma().
@param Channel DMA Channel to configure
@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
@retval EFI_SUCCESS DMA hardware disabled
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
DisableDmaChannel (
IN UINTN Channel,
IN UINT32 SuccessMask,
IN UINT32 ErrorMask
);
#endif

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Omap35xxPkg/Include/Library/OmapLib.h
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/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAPLIB_H__
#define __OMAPLIB_H__
UINT32
EFIAPI
GpioBase (
IN UINTN Port
);
UINT32
EFIAPI
TimerBase (
IN UINTN Timer
);
UINTN
EFIAPI
InterruptVectorForTimer (
IN UINTN TImer
);
UINT32
EFIAPI
UartBase (
IN UINTN Uart
);
#endif // __OMAPLIB_H__

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Omap35xxPkg/Include/Omap3530/Omap3530.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530_H__
#define __OMAP3530_H__
#include "Omap3530Gpio.h"
#include "Omap3530Interrupt.h"
#include "Omap3530Prcm.h"
#include "Omap3530Timer.h"
#include "Omap3530Uart.h"
#include "Omap3530Usb.h"
#include "Omap3530MMCHS.h"
#include "Omap3530I2c.h"
#include "Omap3530PadConfiguration.h"
#include "Omap3530Gpmc.h"
#include "Omap3530Dma.h"
//CONTROL_PBIAS_LITE
#define CONTROL_PBIAS_LITE 0x48002520
#define PBIASLITEVMODE0 BIT0
#define PBIASLITEPWRDNZ0 BIT1
#define PBIASSPEEDCTRL0 BIT2
#define PBIASLITEVMODE1 BIT8
#define PBIASLITEWRDNZ1 BIT9
#endif // __OMAP3530_H__

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/** @file
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530DMA_H__
#define __OMAP3530DMA_H__
#define DMA4_MAX_CHANNEL 31
#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))
#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))
#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))
#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))
#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))
#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))
#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))
#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))
#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))
#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))
#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))
#define DMA4_GCR (0x48056078)
// Channel Source Destination parameters
#define DMA4_CSDP_DATA_TYPE8 0
#define DMA4_CSDP_DATA_TYPE16 1
#define DMA4_CSDP_DATA_TYPE32 2
#define DMA4_CSDP_SRC_PACKED BIT6
#define DMA4_CSDP_SRC_NONPACKED 0
#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)
#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)
#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)
#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)
#define DMA4_CSDP_DST_PACKED BIT13
#define DMA4_CSDP_DST_NONPACKED 0
#define DMA4_CSDP_BURST_EN (0x0 << 14)
#define DMA4_CSDP_BURST_EN16 (0x1 << 14)
#define DMA4_CSDP_BURST_EN32 (0x2 << 14)
#define DMA4_CSDP_BURST_EN64 (0x3 << 14)
#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)
#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)
#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)
#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0
#define DMA4_CSDP_DST_ENDIAN_BIG BIT19
#define DMA4_CSDP_DST_ENDIAN_LITTLE 0
#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0
#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0
// Channel Control
#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f
#define DMA4_CCR_FS_ELEMENT (0 | 0)
#define DMA4_CCR_FS_BLOCK (0 | BIT18)
#define DMA4_CCR_FS_FRAME (BIT5 | 0)
#define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
#define DMA4_CCR_READ_PRIORITY_HIGH BIT6
#define DMA4_CCR_READ_PRIORITY_LOW 0
#define DMA4_CCR_ENABLE BIT7
#define DMA4_CCR_DISABLE 0
#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
#define DMA4_CCR_SUSPEND_SENSITIVE 0
#define DMA4_CCR_RD_ACTIVE BIT9
#define DMA4_CCR_WR_ACTIVE BIT10
#define DMA4_CCR_SRC_AMODE (0 | 0)
#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)
#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)
#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)
#define DMA4_CCR_DST_AMODE (0 | 0)
#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
#define DMA4_CCR_CONST_FILL_ENABLE BIT16
#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17
#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
#define DMA4_CSR_DROP BIT1
#define DMA4_CSR_HALF BIT2
#define DMA4_CSR_FRAME BIT3
#define DMA4_CSR_LAST BIT4
#define DMA4_CSR_BLOCK BIT5
#define DMA4_CSR_SYNC BIT6
#define DMA4_CSR_PKT BIT7
#define DMA4_CSR_TRANS_ERR BIT8
#define DMA4_CSR_SECURE_ERR BIT9
#define DMA4_CSR_SUPERVISOR_ERR BIT10
#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11
#define DMA4_CSR_DRAIN_END BIT12
#define DMA4_CSR_RESET 0x1FE
#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)
// same mapping as CSR except for SYNC. Enable all since we are polling
#define DMA4_CICR_ENABLE_ALL 0x1FBE
#endif

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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530GPIO_H__
#define __OMAP3530GPIO_H__
#define GPIO1_BASE (0x48310000)
#define GPIO2_BASE (0x49050000)
#define GPIO3_BASE (0x49052000)
#define GPIO4_BASE (0x49054000)
#define GPIO5_BASE (0x49056000)
#define GPIO6_BASE (0x49058000)
#define GPIO_SYSCONFIG (0x0010)
#define GPIO_SYSSTATUS (0x0014)
#define GPIO_IRQSTATUS1 (0x0018)
#define GPIO_IRQENABLE1 (0x001C)
#define GPIO_WAKEUPENABLE (0x0020)
#define GPIO_IRQSTATUS2 (0x0028)
#define GPIO_IRQENABLE2 (0x002C)
#define GPIO_CTRL (0x0030)
#define GPIO_OE (0x0034)
#define GPIO_DATAIN (0x0038)
#define GPIO_DATAOUT (0x003C)
#define GPIO_LEVELDETECT0 (0x0040)
#define GPIO_LEVELDETECT1 (0x0044)
#define GPIO_RISINGDETECT (0x0048)
#define GPIO_FALLINGDETECT (0x004C)
#define GPIO_DEBOUNCENABLE (0x0050)
#define GPIO_DEBOUNCINGTIME (0x0054)
#define GPIO_CLEARIRQENABLE1 (0x0060)
#define GPIO_SETIRQENABLE1 (0x0064)
#define GPIO_CLEARIRQENABLE2 (0x0070)
#define GPIO_SETIRQENABLE2 (0x0074)
#define GPIO_CLEARWKUENA (0x0080)
#define GPIO_SETWKUENA (0x0084)
#define GPIO_CLEARDATAOUT (0x0090)
#define GPIO_SETDATAOUT (0x0094)
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
#define GPIO_CTRL_DISABLEMODULE_MASK BIT0
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
#define GPIO_OE_MASK(x) (1UL << (x))
#define GPIO_OE_OUTPUT(x) (0UL << (x))
#define GPIO_OE_INPUT(x) (1UL << (x))
#define GPIO_DATAIN_MASK(x) (1UL << (x))
#define GPIO_DATAOUT_MASK(x) (1UL << (x))
#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
#endif // __OMAP3530GPIO_H__

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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530GPMC_H__
#define __OMAP3530GPMC_H__
#define GPMC_BASE (0x6E000000)
//GPMC NAND definitions.
#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
#define SMARTIDLEMODE (0x2UL << 3)
#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
#define TIMEOUTENABLE BIT0
#define TIMEOUTDISABLE (0x0UL << 0)
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
#define GPMC_CONFIG (GPMC_BASE + 0x50)
#define WRITEPROTECT_HIGH BIT4
#define WRITEPROTECT_LOW (0x0UL << 4)
#define GPMC_STATUS (GPMC_BASE + 0x54)
#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
#define DEVICETYPE_NOR (0x0UL << 10)
#define DEVICETYPE_NAND (0x2UL << 10)
#define DEVICESIZE_X8 (0x0UL << 12)
#define DEVICESIZE_X16 BIT12
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
#define CSONTIME (0x0UL << 0)
#define CSRDOFFTIME (0x14UL << 8)
#define CSWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
#define ADVRDOFFTIME (0x14UL << 8)
#define ADVWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
#define OEONTIME BIT0
#define OEOFFTIME (0xFUL << 8)
#define WEONTIME BIT16
#define WEOFFTIME (0xFUL << 24)
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
#define RDCYCLETIME (0x14UL << 0)
#define WRCYCLETIME (0x14UL << 8)
#define RDACCESSTIME (0xCUL << 16)
#define PAGEBURSTACCESSTIME BIT24
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
#define CYCLE2CYCLESAMECSEN BIT7
#define CYCLE2CYCLEDELAY (0xAUL << 8)
#define WRDATAONADMUXBUS (0xFUL << 16)
#define WRACCESSTIME BIT24
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
#define BASEADDRESS (0x30UL << 0)
#define CSVALID BIT6
#define MASKADDRESS_128MB (0x8UL << 8)
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
#define ECCENABLE BIT0
#define ECCDISABLE (0x0UL << 0)
#define ECCCS_0 (0x0UL << 1)
#define ECC16B BIT7
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
#define ECCPOINTER_REG1 BIT0
#define ECCCLEAR BIT8
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
#define ECCSIZE0_512BYTES (0xFFUL << 12)
#define ECCSIZE1_512BYTES (0xFFUL << 22)
#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
#endif //__OMAP3530GPMC_H__

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Omap35xxPkg/Include/Omap3530/Omap3530I2c.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530I2C_H__
#define __OMAP3530I2C_H__
//I2C register definitions.
#define I2C1BASE 0x48070000
#define I2C_IE (I2C1BASE + 0x4)
#define XRDY_IE BIT4
#define RRDY_IE BIT3
#define ARDY_IE BIT2
#define NACK_IE BIT1
#define I2C_STAT (I2C1BASE + 0x8)
#define BB BIT12
#define XRDY BIT4
#define RRDY BIT3
#define ARDY BIT2
#define NACK BIT1
#define I2C_WE (I2C1BASE + 0xC)
#define I2C_SYSS (I2C1BASE + 0x10)
#define I2C_BUF (I2C1BASE + 0x14)
#define I2C_CNT (I2C1BASE + 0x18)
#define I2C_DATA (I2C1BASE + 0x1C)
#define I2C_SYSC (I2C1BASE + 0x20)
#define I2C_CON (I2C1BASE + 0x24)
#define STT BIT0
#define STP BIT1
#define XSA BIT8
#define TRX BIT9
#define MST BIT10
#define I2C_EN BIT15
#define I2C_OA0 (I2C1BASE + 0x28)
#define I2C_SA (I2C1BASE + 0x2C)
#define I2C_PSC (I2C1BASE + 0x30)
#define I2C_SCLL (I2C1BASE + 0x34)
#define I2C_SCLH (I2C1BASE + 0x38)
#define I2C_SYSTEST (I2C1BASE + 0x3C)
#define I2C_BUFSTAT (I2C1BASE + 0x40)
#define I2C_OA1 (I2C1BASE + 0x44)
#define I2C_OA2 (I2C1BASE + 0x48)
#define I2C_OA3 (I2C1BASE + 0x4C)
#define I2C_ACTOA (I2C1BASE + 0x50)
#define I2C_SBLOCK (I2C1BASE + 0x54)
#endif //__OMAP3530I2C_H__

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Omap35xxPkg/Include/Omap3530/Omap3530Interrupt.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530INTERRUPT_H__
#define __OMAP3530INTERRUPT_H__
#include <Library/PcdLib.h>
#define INTERRUPT_BASE (PcdGet32 (PcdInterruptBaseAddress))
#define INT_NROF_VECTORS (96)
#define MAX_VECTOR (INT_NROF_VECTORS - 1)
#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
#define INTCPS_ILR_FIQ BIT0
#define INTCPS_SIR_IRQ_MASK (0x7F)
#define INTCPS_CONTROL_NEWIRQAGR BIT0
#define INTCPS_CONTROL_NEWFIQAGR BIT1
#endif // __OMAP3530INTERRUPT_H__

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Omap35xxPkg/Include/Omap3530/Omap3530MMCHS.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530SDIO_H__
#define __OMAP3530SDIO_H__
//MMC/SD/SDIO1 register definitions.
#define MMCHS1BASE 0x4809C000
#define MMC_REFERENCE_CLK (96000000)
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
#define SOFTRESET BIT1
#define ENAWAKEUP BIT2
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
#define RESETDONE_MASK BIT0
#define RESETDONE BIT0
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
#define MMCHS_CON (MMCHS1BASE + 0x2C)
#define OD BIT0
#define NOINIT (0x0UL << 1)
#define INIT BIT1
#define HR BIT2
#define STR BIT3
#define MODE BIT4
#define DW8_1_4_BIT (0x0UL << 5)
#define DW8_8_BIT BIT5
#define MIT BIT6
#define CDP BIT7
#define WPP BIT8
#define CTPL BIT11
#define CEATA_OFF (0x0UL << 12)
#define CEATA_ON BIT12
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
#define MMCHS_BLK (MMCHS1BASE + 0x104)
#define BLEN_512BYTES (0x200UL << 0)
#define MMCHS_ARG (MMCHS1BASE + 0x108)
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
#define DE_ENABLE BIT0
#define BCE_ENABLE BIT1
#define ACEN_ENABLE BIT2
#define DDIR_READ BIT4
#define DDIR_WRITE (0x0UL << 4)
#define MSBS_SGLEBLK (0x0UL << 5)
#define MSBS_MULTBLK BIT5
#define RSP_TYPE_MASK (0x3UL << 16)
#define RSP_TYPE_136BITS BIT16
#define RSP_TYPE_48BITS (0x2UL << 16)
#define CCCE_ENABLE BIT19
#define CICE_ENABLE BIT20
#define DP_ENABLE BIT21
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
#define MMCHS_DATA (MMCHS1BASE + 0x120)
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
#define CMDI_MASK BIT0
#define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED BIT0
#define DATI_MASK BIT1
#define DATI_ALLOWED (0x0UL << 1)
#define DATI_NOT_ALLOWED BIT1
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
#define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT BIT1
#define SDBP_MASK BIT8
#define SDBP_OFF (0x0UL << 8)
#define SDBP_ON BIT8
#define SDVS_1_8_V (0x5UL << 9)
#define SDVS_3_0_V (0x6UL << 9)
#define IWE BIT24
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
#define ICE BIT0
#define ICS_MASK BIT1
#define ICS BIT1
#define CEN BIT2
#define CLKD_MASK (0x3FFUL << 6)
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
#define CLKD_400KHZ (0xF0UL)
#define DTO_MASK (0xFUL << 16)
#define DTO_VAL (0xEUL << 16)
#define SRA BIT24
#define SRC_MASK BIT25
#define SRC BIT25
#define SRD BIT26
#define MMCHS_STAT (MMCHS1BASE + 0x130)
#define CC BIT0
#define TC BIT1
#define BWR BIT4
#define BRR BIT5
#define ERRI BIT15
#define CTO BIT16
#define DTO BIT20
#define DCRC BIT21
#define DEB BIT22
#define MMCHS_IE (MMCHS1BASE + 0x134)
#define CC_EN BIT0
#define TC_EN BIT1
#define BWR_EN BIT4
#define BRR_EN BIT5
#define CTO_EN BIT16
#define CCRC_EN BIT17
#define CEB_EN BIT18
#define CIE_EN BIT19
#define DTO_EN BIT20
#define DCRC_EN BIT21
#define DEB_EN BIT22
#define CERR_EN BIT28
#define BADA_EN BIT29
#define MMCHS_ISE (MMCHS1BASE + 0x138)
#define CC_SIGEN BIT0
#define TC_SIGEN BIT1
#define BWR_SIGEN BIT4
#define BRR_SIGEN BIT5
#define CTO_SIGEN BIT16
#define CCRC_SIGEN BIT17
#define CEB_SIGEN BIT18
#define CIE_SIGEN BIT19
#define DTO_SIGEN BIT20
#define DCRC_SIGEN BIT21
#define DEB_SIGEN BIT22
#define CERR_SIGEN BIT28
#define BADA_SIGEN BIT29
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
#define VS30 BIT25
#define VS18 BIT26
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
#define CMD0 INDX(0)
#define CMD0_INT_EN (CC_EN | CEB_EN)
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define ACMD6 (INDX(6) | RSP_TYPE_48BITS)
#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#endif //__OMAP3530SDIO_H__

297
Omap35xxPkg/Include/Omap3530/Omap3530PadConfiguration.h
View File

@@ -1,297 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530_PAD_CONFIGURATION_H__
#define __OMAP3530_PAD_CONFIGURATION_H__
#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
//Pin definition
#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
#define SYS_BOOT0 (SYSTEM_CONTROL_MODULE_BASE + 0xA0A)
#define SYS_BOOT1 (SYSTEM_CONTROL_MODULE_BASE + 0xA0C)
#define SYS_BOOT3 (SYSTEM_CONTROL_MODULE_BASE + 0xA10)
#define SYS_BOOT4 (SYSTEM_CONTROL_MODULE_BASE + 0xA12)
#define SYS_BOOT5 (SYSTEM_CONTROL_MODULE_BASE + 0xA14)
#define SYS_BOOT6 (SYSTEM_CONTROL_MODULE_BASE + 0xA16)
//Mux modes
#define MUXMODE0 (0x0UL)
#define MUXMODE1 (0x1UL)
#define MUXMODE2 (0x2UL)
#define MUXMODE3 (0x3UL)
#define MUXMODE4 (0x4UL)
#define MUXMODE5 (0x5UL)
#define MUXMODE6 (0x6UL)
#define MUXMODE7 (0x7UL)
//Pad configuration register.
#define PAD_CONFIG_MASK (0xFFFFUL)
#define MUXMODE_OFFSET 0
#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
#define PULL_CONFIG_OFFSET 3
#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
#define INPUTENABLE_OFFSET 8
#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
#define OFFMODE_VALUE_OFFSET 9
#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
#define WAKEUP_OFFSET 14
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
#define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)
#define PULL_UP_SELECTED (BIT1 | BIT0)
#define PULL_DISABLED (0x0UL << 0)
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
typedef struct {
UINTN Pin;
UINTN MuxMode;
UINTN PullConfig;
UINTN InputEnable;
} PAD_CONFIGURATION;
#endif //__OMAP3530_PAD_CONFIGURATION_H__

159
Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530PRCM_H__
#define __OMAP3530PRCM_H__
#define CM_FCLKEN1_CORE (0x48004A00)
#define CM_FCLKEN3_CORE (0x48004A08)
#define CM_ICLKEN1_CORE (0x48004A10)
#define CM_ICLKEN3_CORE (0x48004A18)
#define CM_CLKEN2_PLL (0x48004D04)
#define CM_CLKSEL4_PLL (0x48004D4C)
#define CM_CLKSEL5_PLL (0x48004D50)
#define CM_FCLKEN_USBHOST (0x48005400)
#define CM_ICLKEN_USBHOST (0x48005410)
#define CM_CLKSTST_USBHOST (0x4800544c)
//Wakeup clock defintion
#define CM_FCLKEN_WKUP (0x48004C00)
#define CM_ICLKEN_WKUP (0x48004C10)
//Peripheral clock definition
#define CM_FCLKEN_PER (0x48005000)
#define CM_ICLKEN_PER (0x48005010)
#define CM_CLKSEL_PER (0x48005040)
//Reset management definition
#define PRM_RSTCTRL (0x48307250)
#define PRM_RSTST (0x48307258)
//CORE clock
#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
#define CM_CLKEN_ENABLE (7UL << 0)
#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
//Wakeup functional clock
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Wakeup interface clock
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Peripheral functional clock
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
//Peripheral interface clock
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
//Timer source clock selection
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
//Reset management (Global and Cold reset)
#define RST_GS BIT1
#define RST_DPLL3 BIT2
#define GLOBAL_SW_RST BIT1
#define GLOBAL_COLD_RST (0x0UL << 0)
#endif // __OMAP3530PRCM_H__

76
Omap35xxPkg/Include/Omap3530/Omap3530Timer.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530TIMER_H__
#define __OMAP3530TIMER_H__
#define GPTIMER1_BASE (0x48313000)
#define GPTIMER2_BASE (0x49032000)
#define GPTIMER3_BASE (0x49034000)
#define GPTIMER4_BASE (0x49036000)
#define GPTIMER5_BASE (0x49038000)
#define GPTIMER6_BASE (0x4903A000)
#define GPTIMER7_BASE (0x4903C000)
#define GPTIMER8_BASE (0x4903E000)
#define GPTIMER9_BASE (0x49040000)
#define GPTIMER10_BASE (0x48086000)
#define GPTIMER11_BASE (0x48088000)
#define GPTIMER12_BASE (0x48304000)
#define WDTIMER2_BASE (0x48314000)
#define GPTIMER_TIOCP_CFG (0x0010)
#define GPTIMER_TISTAT (0x0014)
#define GPTIMER_TISR (0x0018)
#define GPTIMER_TIER (0x001C)
#define GPTIMER_TWER (0x0020)
#define GPTIMER_TCLR (0x0024)
#define GPTIMER_TCRR (0x0028)
#define GPTIMER_TLDR (0x002C)
#define GPTIMER_TTGR (0x0030)
#define GPTIMER_TWPS (0x0034)
#define GPTIMER_TMAR (0x0038)
#define GPTIMER_TCAR1 (0x003C)
#define GPTIMER_TSICR (0x0040)
#define GPTIMER_TCAR2 (0x0044)
#define GPTIMER_TPIR (0x0048)
#define GPTIMER_TNIR (0x004C)
#define GPTIMER_TCVR (0x0050)
#define GPTIMER_TOCR (0x0054)
#define GPTIMER_TOWR (0x0058)
#define WSPR (0x048)
#define TISR_TCAR_IT_FLAG_MASK BIT2
#define TISR_OVF_IT_FLAG_MASK BIT1
#define TISR_MAT_IT_FLAG_MASK BIT0
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
#define TISR_TCAR_IT_FLAG_CLEAR BIT2
#define TISR_OVF_IT_FLAG_CLEAR BIT1
#define TISR_MAT_IT_FLAG_CLEAR BIT0
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
#define TCLR_AR_AUTORELOAD BIT1
#define TCLR_AR_ONESHOT (0UL << 1)
#define TCLR_ST_ON BIT0
#define TCLR_ST_OFF (0UL << 0)
#define TIER_TCAR_IT_ENABLE (BIT2
#define TIER_TCAR_IT_DISABLE (0UL << 2)
#define TIER_OVF_IT_ENABLE BIT1
#define TIER_OVF_IT_DISABLE (0UL << 1)
#define TIER_MAT_IT_ENABLE BIT0
#define TIER_MAT_IT_DISABLE (0UL << 0)
#endif // __OMAP3530TIMER_H__

48
Omap35xxPkg/Include/Omap3530/Omap3530Uart.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530UART_H__
#define __OMAP3530UART_H__
#define UART1_BASE (0x4806A000)
#define UART2_BASE (0x4806C000)
#define UART3_BASE (0x49020000)
#define UART_DLL_REG (0x0000)
#define UART_RBR_REG (0x0000)
#define UART_THR_REG (0x0000)
#define UART_DLH_REG (0x0004)
#define UART_FCR_REG (0x0008)
#define UART_LCR_REG (0x000C)
#define UART_MCR_REG (0x0010)
#define UART_LSR_REG (0x0014)
#define UART_MDR1_REG (0x0020)
#define UART_FCR_TX_FIFO_CLEAR BIT2
#define UART_FCR_RX_FIFO_CLEAR BIT1
#define UART_FCR_FIFO_ENABLE BIT0
#define UART_LCR_DIV_EN_ENABLE BIT7
#define UART_LCR_DIV_EN_DISABLE (0UL << 7)
#define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0)
#define UART_MCR_RTS_FORCE_ACTIVE BIT1
#define UART_MCR_DTR_FORCE_ACTIVE BIT0
#define UART_LSR_TX_FIFO_E_MASK BIT5
#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
#define UART_LSR_TX_FIFO_E_EMPTY BIT5
#define UART_LSR_RX_FIFO_E_MASK BIT0
#define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0
#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
// BIT2:BIT0
#define UART_MDR1_MODE_SELECT_DISABLE (7UL)
#define UART_MDR1_MODE_SELECT_UART_16X (0UL)
#endif // __OMAP3530UART_H__

42
Omap35xxPkg/Include/Omap3530/Omap3530Usb.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3530USB_H__
#define __OMAP3530USB_H__
#define USB_BASE (0x48060000)
#define UHH_SYSCONFIG (USB_BASE + 0x4010)
#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
#define UHH_SYSSTATUS (USB_BASE + 0x4014)
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY BIT12
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT3
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define UHH_SYSCONFIG_SOFTRESET BIT1
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
#define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
#endif // __OMAP3530USB_H__

74
Omap35xxPkg/Include/TPS65950.h
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/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __TPS65950_H__
#define __TPS65950_H__
#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF)
#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF)
#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))
// I2C Address group
#define I2C_ADDR_GRP_ID1 0x48
#define I2C_ADDR_GRP_ID2 0x49
#define I2C_ADDR_GRP_ID3 0x4A
#define I2C_ADDR_GRP_ID4 0x4B
#define I2C_ADDR_GRP_ID5 0x12
// MMC definitions.
#define VMMC1_DEV_GRP 0x82
#define DEV_GRP_P1 BIT5
#define VMMC1_DEDICATED_REG 0x85
#define VSEL_1_85V 0x0
#define VSEL_2_85V 0x1
#define VSEL_3_00V 0x2
#define VSEL_3_15V 0x3
#define TPS65950_GPIO_CTRL 0xaa //I2C_ADDR_GRP_ID2
#define CARD_DETECT_ENABLE (BIT2 | BIT0) // GPIO ON + GPIO CD1 enabled
#define GPIODATAIN1 0x98 //I2C_ADDR_GRP_ID2
#define CARD_DETECT_BIT BIT0
// LEDEN register
#define LEDEN 0xEE
#define LEDAON BIT0
#define LEDBON BIT1
#define LEDAPWM BIT4
#define LEDBPWM BIT5
// RTC registers
#define SECONDS_REG 0x1C
#define MINUTES_REG 0x1D
#define HOURS_REG 0x1E
#define DAYS_REG 0x1F
#define MONTHS_REG 0x20
#define YEARS_REG 0x21
#define WEEKS_REG 0x22
#define RTC_CTRL_REG 0x29
// USB PHY power
#define VAUX2_DEDICATED 0x79
#define VAUX2_DEV_GRP 0x76
#define VAUX_DEV_GRP_NONE 0x00
#define VAUX_DEV_GRP_P1 0x20
#define VAUX_DEV_GRP_P2 0x40
#define VAUX_DEV_GRP_P3 0x80
#define VAUX_DEDICATED_18V 0x05
// Display subsystem
#define VPLL2_DEDICATED 0x91
#define VPLL2_DEV_GRP 0x8E
#define GPIODATADIR1 0x9B
#define SETGPIODATAOUT1 0xA4
#endif //__TPS65950_H__

396
Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
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/** @file
Handle OMAP35xx interrupt controller
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/ArmLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h>
#include <Omap3530/Omap3530.h>
//
// Notifications
//
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];
/**
Shutdown our hardware
DXE Core will disable interrupts and turn off the timer and disable interrupts
after all the event handlers have run.
@param[in] Event The Event that is being processed
@param[in] Context Event Context
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
// Disable all interrupts
MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
// Add code here to disable all FIQs as debugger may have turned one on
}
/**
Register Handler for the specified interrupt source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param Handler Callback for interrupt. NULL to unregister
@retval EFI_SUCCESS Source was updated to support Handler.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {
// This vector has been programmed as FIQ so we can't use it for IRQ
// EFI does not use FIQ, but the debugger can use it to check for
// ctrl-c. So this ASSERT means you have a conflict with the debug agent
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
return EFI_ALREADY_STARTED;
}
gRegisteredInterruptHandlers[Source] = Handler;
return This->EnableInterruptSource(This, Source);
}
/**
Enable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt enabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINTN Bank;
UINTN Bit;
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
return EFI_SUCCESS;
}
/**
Disable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt disabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
DisableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINTN Bank;
UINTN Bit;
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
return EFI_SUCCESS;
}
/**
Return current state of interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param InterruptState TRUE: source enabled, FALSE: source disabled.
@retval EFI_SUCCESS InterruptState is valid
@retval EFI_DEVICE_ERROR InterruptState is not valid
**/
EFI_STATUS
EFIAPI
GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
UINTN Bank;
UINTN Bit;
if (InterruptState == NULL) {
return EFI_INVALID_PARAMETER;
}
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
}
return EFI_SUCCESS;
}
/**
Signal to the hardware that the End Of Intrrupt state
has been reached.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
return EFI_SUCCESS;
}
/**
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
@return None
**/
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 Vector;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
// Needed to prevent infinite nesting when Time Driver lowers TPL
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
InterruptHandler (Vector, SystemContext);
}
// Needed to clear after running the handler
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
}
//
// Making this global saves a few bytes in image size
//
EFI_HANDLE gHardwareInterruptHandle = NULL;
//
// The protocol instance produced by this driver
//
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
RegisterInterruptSource,
EnableInterruptSource,
DisableInterruptSource,
GetInterruptSourceState,
EndOfInterrupt
};
STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC
VOID
EFIAPI
CpuArchEventProtocolNotify (
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: gBS->LocateProtocol() - %r\n", __FUNCTION__,
Status));
ASSERT (FALSE);
return;
}
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
ASSERT (FALSE);
return;
}
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ,
IrqInterruptHandler);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
ASSERT (FALSE);
return;
}
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_EVENT CpuArchEvent;
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
// Make sure all interrupts are disabled by default.
MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL);
ASSERT_EFI_ERROR(Status);
//
// Install the interrupt handler as soon as the CPU arch protocol appears.
//
CpuArchEvent = EfiCreateProtocolNotifyEvent (
&gEfiCpuArchProtocolGuid,
TPL_CALLBACK,
CpuArchEventProtocolNotify,
NULL,
&mCpuArchProtocolNotifyEventRegistration
);
ASSERT (CpuArchEvent != NULL);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
if (EFI_ERROR (Status)) {
ASSERT_EFI_ERROR (Status);
gBS->CloseEvent (CpuArchEvent);
}
return Status;
}

48
Omap35xxPkg/InterruptDxe/InterruptDxe.inf
View File

@@ -1,48 +0,0 @@
#/** @file
#
# Interrupt DXE driver
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Omap35xxBoardInterruptDxe
FILE_GUID = 23eed05d-1b93-4a1a-8e1b-931d69e37952
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InterruptDxeInitialize
[Sources.common]
HardwareInterrupt.c
[Packages]
ArmPkg/ArmPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
BaseLib
UefiLib
UefiBootServicesTableLib
DebugLib
PrintLib
UefiDriverEntryPoint
IoLib
ArmLib
[Protocols]
gHardwareInterruptProtocolGuid ## PRODUCES
gEfiCpuArchProtocolGuid ## CONSUMES ## NOTIFY
[FixedPcd.common]
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress
[Depex]
TRUE

439
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c
View File

@@ -1,439 +0,0 @@
/** @file
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Guid/GlobalVariable.h>
#include "LcdGraphicsOutputDxe.h"
extern BOOLEAN mDisplayInitialized;
//
// Function Definitions
//
STATIC
EFI_STATUS
VideoCopyNoHorizontalOverlap (
IN UINTN BitsPerPixel,
IN volatile VOID *FrameBufferBase,
IN UINT32 HorizontalResolution,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINTN SourceLine;
UINTN DestinationLine;
UINTN WidthInBytes;
UINTN LineCount;
INTN Step;
VOID *SourceAddr;
VOID *DestinationAddr;
if( DestinationY <= SourceY ) {
// scrolling up (or horizontally but without overlap)
SourceLine = SourceY;
DestinationLine = DestinationY;
Step = 1;
} else {
// scrolling down
SourceLine = SourceY + Height;
DestinationLine = DestinationY + Height;
Step = -1;
}
WidthInBytes = Width * 2;
for( LineCount = 0; LineCount < Height; LineCount++ ) {
// Update the start addresses of source & destination using 16bit pointer arithmetic
SourceAddr = (VOID *)((UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX );
DestinationAddr = (VOID *)((UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX);
// Copy the entire line Y from video ram to the temp buffer
CopyMem( DestinationAddr, SourceAddr, WidthInBytes);
// Update the line numbers
SourceLine += Step;
DestinationLine += Step;
}
return Status;
}
STATIC
EFI_STATUS
VideoCopyHorizontalOverlap (
IN UINTN BitsPerPixel,
IN volatile VOID *FrameBufferBase,
UINT32 HorizontalResolution,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT16 *PixelBuffer16bit;
UINT16 *SourcePixel16bit;
UINT16 *DestinationPixel16bit;
UINT32 SourcePixelY;
UINT32 DestinationPixelY;
UINTN SizeIn16Bits;
// Allocate a temporary buffer
PixelBuffer16bit = (UINT16 *) AllocatePool((Height * Width) * sizeof(UINT16));
if (PixelBuffer16bit == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto EXIT;
}
// Access each pixel inside the source area of the Video Memory and copy it to the temp buffer
SizeIn16Bits = Width * 2;
for (SourcePixelY = SourceY, DestinationPixel16bit = PixelBuffer16bit;
SourcePixelY < SourceY + Height;
SourcePixelY++, DestinationPixel16bit += Width)
{
// Calculate the source address:
SourcePixel16bit = (UINT16 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX;
// Copy the entire line Y from Video to the temp buffer
CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits);
}
// Copy from the temp buffer into the destination area of the Video Memory
for (DestinationPixelY = DestinationY, SourcePixel16bit = PixelBuffer16bit;
DestinationPixelY < DestinationY + Height;
DestinationPixelY++, SourcePixel16bit += Width)
{
// Calculate the target address:
DestinationPixel16bit = (UINT16 *)FrameBufferBase + (DestinationPixelY * HorizontalResolution + DestinationX);
// Copy the entire line Y from the temp buffer to Video
CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits);
}
// Free the allocated memory
FreePool((VOID *) PixelBuffer16bit);
EXIT:
return Status;
}
STATIC
EFI_STATUS
BltVideoFill (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel, OPTIONAL
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
)
{
EFI_PIXEL_BITMASK* PixelInformation;
EFI_STATUS Status;
UINT32 HorizontalResolution;
VOID *FrameBufferBase;
UINT16 *DestinationPixel16bit;
UINT16 Pixel16bit;
UINT32 DestinationPixelX;
UINT32 DestinationLine;
Status = EFI_SUCCESS;
PixelInformation = &This->Mode->Info->PixelInformation;
FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
HorizontalResolution = This->Mode->Info->HorizontalResolution;
// Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel
Pixel16bit = (UINT16) (
( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask )
| ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask )
| ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask )
);
// Copy the SourcePixel into every pixel inside the target rectangle
for (DestinationLine = DestinationY;
DestinationLine < DestinationY + Height;
DestinationLine++)
{
for (DestinationPixelX = DestinationX;
DestinationPixelX < DestinationX + Width;
DestinationPixelX++)
{
// Calculate the target address:
DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX;
// Copy the pixel into the new target
*DestinationPixel16bit = Pixel16bit;
}
}
return Status;
}
STATIC
EFI_STATUS
BltVideoToBltBuffer (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
)
{
EFI_STATUS Status;
UINT32 HorizontalResolution;
EFI_PIXEL_BITMASK *PixelInformation;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiDestinationPixel;
VOID *FrameBufferBase;
UINT16 *SourcePixel16bit;
UINT16 Pixel16bit;
UINT32 SourcePixelX;
UINT32 SourceLine;
UINT32 DestinationPixelX;
UINT32 DestinationLine;
UINT32 BltBufferHorizontalResolution;
Status = EFI_SUCCESS;
PixelInformation = &This->Mode->Info->PixelInformation;
HorizontalResolution = This->Mode->Info->HorizontalResolution;
FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
// Delta is not zero and it is different from the width.
// Divide it by the size of a pixel to find out the buffer's horizontal resolution.
BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
} else {
BltBufferHorizontalResolution = Width;
}
// Access each pixel inside the Video Memory
for (SourceLine = SourceY, DestinationLine = DestinationY;
SourceLine < SourceY + Height;
SourceLine++, DestinationLine++)
{
for (SourcePixelX = SourceX, DestinationPixelX = DestinationX;
SourcePixelX < SourceX + Width;
SourcePixelX++, DestinationPixelX++)
{
// Calculate the source and target addresses:
SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX;
EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX;
// Snapshot the pixel from the video buffer once, to speed up the operation.
// If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations.
Pixel16bit = *SourcePixel16bit;
// Copy the pixel into the new target
EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 8 );
EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) >> 3 );
EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 3 );
}
}
return Status;
}
STATIC
EFI_STATUS
BltBufferToVideo (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
)
{
EFI_STATUS Status;
UINT32 HorizontalResolution;
EFI_PIXEL_BITMASK *PixelInformation;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel;
VOID *FrameBufferBase;
UINT16 *DestinationPixel16bit;
UINT32 SourcePixelX;
UINT32 SourceLine;
UINT32 DestinationPixelX;
UINT32 DestinationLine;
UINT32 BltBufferHorizontalResolution;
Status = EFI_SUCCESS;
PixelInformation = &This->Mode->Info->PixelInformation;
HorizontalResolution = This->Mode->Info->HorizontalResolution;
FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
// Delta is not zero and it is different from the width.
// Divide it by the size of a pixel to find out the buffer's horizontal resolution.
BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
} else {
BltBufferHorizontalResolution = Width;
}
// Access each pixel inside the BltBuffer Memory
for (SourceLine = SourceY, DestinationLine = DestinationY;
SourceLine < SourceY + Height;
SourceLine++, DestinationLine++) {
for (SourcePixelX = SourceX, DestinationPixelX = DestinationX;
SourcePixelX < SourceX + Width;
SourcePixelX++, DestinationPixelX++)
{
// Calculate the source and target addresses:
EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX;
DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX;
// Copy the pixel into the new target
// Only the most significant bits will be copied across:
// To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits
*DestinationPixel16bit = (UINT16) (
( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask )
| ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask )
| ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask )
);
}
}
return Status;
}
STATIC
EFI_STATUS
BltVideoToVideo (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
)
{
EFI_STATUS Status;
UINT32 HorizontalResolution;
UINTN BitsPerPixel;
VOID *FrameBufferBase;
BitsPerPixel = 16;
HorizontalResolution = This->Mode->Info->HorizontalResolution;
FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
//
// BltVideo to BltVideo:
//
// Source is the Video Memory,
// Destination is the Video Memory
FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase));
// The UEFI spec currently states:
// "There is no limitation on the overlapping of the source and destination rectangles"
// Therefore, we must be careful to avoid overwriting the source data
if( SourceY == DestinationY ) {
// Copying within the same height, e.g. horizontal shift
if( SourceX == DestinationX ) {
// Nothing to do
Status = EFI_SUCCESS;
} else if( ((SourceX>DestinationX)?(SourceX - DestinationX):(DestinationX - SourceX)) < Width ) {
// There is overlap
Status = VideoCopyHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
} else {
// No overlap
Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
}
} else {
// Copying from different heights
Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height );
}
return Status;
}
EFI_STATUS
EFIAPI
LcdGraphicsBlt (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
)
{
EFI_STATUS Status;
LCD_INSTANCE *Instance;
Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
if (!mDisplayInitialized) {
InitializeDisplay (Instance);
}
switch (BltOperation) {
case EfiBltVideoFill:
Status = BltVideoFill (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
break;
case EfiBltVideoToBltBuffer:
Status = BltVideoToBltBuffer (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
break;
case EfiBltBufferToVideo:
Status = BltBufferToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
break;
case EfiBltVideoToVideo:
Status = BltVideoToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta);
break;
case EfiGraphicsOutputBltOperationMax:
default:
DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: Invalid Operation\n"));
Status = EFI_INVALID_PARAMETER;
break;
}
return Status;
}

394
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c
View File

@@ -1,394 +0,0 @@
/** @file
Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "LcdGraphicsOutputDxe.h"
BOOLEAN mDisplayInitialized = FALSE;
LCD_MODE LcdModes[] = {
{
0, 640, 480,
9, 4,
96, 16, 48,
2, 10, 33
},
{
1, 800, 600,
11, 2,
120, 56, 64,
5, 37, 22
},
{
2, 1024, 768,
6, 2,
96, 16, 48,
2, 10, 33
},
};
LCD_INSTANCE mLcdTemplate = {
LCD_INSTANCE_SIGNATURE,
NULL, // Handle
{ // ModeInfo
0, // Version
0, // HorizontalResolution
0, // VerticalResolution
PixelBltOnly, // PixelFormat
{
0xF800, //RedMask;
0x7E0, //GreenMask;
0x1F, //BlueMask;
0x0//ReservedMask
}, // PixelInformation
0, // PixelsPerScanLine
},
{ // Mode
3, // MaxMode;
0, // Mode;
NULL, // Info;
0, // SizeOfInfo;
0, // FrameBufferBase;
0 // FrameBufferSize;
},
{ // Gop
LcdGraphicsQueryMode, // QueryMode
LcdGraphicsSetMode, // SetMode
LcdGraphicsBlt, // Blt
NULL // *Mode
},
{ // DevicePath
{
{
HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
{ (UINT8) (sizeof(VENDOR_DEVICE_PATH)), (UINT8) ((sizeof(VENDOR_DEVICE_PATH)) >> 8) },
},
// Hardware Device Path for Lcd
EFI_CALLER_ID_GUID // Use the driver's GUID
},
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{ sizeof(EFI_DEVICE_PATH_PROTOCOL), 0}
}
}
};
EFI_STATUS
LcdInstanceContructor (
OUT LCD_INSTANCE** NewInstance
)
{
LCD_INSTANCE* Instance;
Instance = AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate);
if (Instance == NULL) {
return EFI_OUT_OF_RESOURCES;
}
Instance->Gop.Mode = &Instance->Mode;
Instance->Mode.Info = &Instance->ModeInfo;
*NewInstance = Instance;
return EFI_SUCCESS;
}
EFI_STATUS
LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
OUT UINTN* VramSize
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINTN MaxSize;
MaxSize = 0x500000;
*VramSize = MaxSize;
// Allocate VRAM from DRAM
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES((MaxSize)), VramBaseAddress);
if (EFI_ERROR(Status)) {
return Status;
}
// Ensure the Cpu architectural protocol is already installed
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
// Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.
Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
if (EFI_ERROR(Status)) {
gBS->FreePool (VramBaseAddress);
return Status;
}
return EFI_SUCCESS;
}
EFI_STATUS
DssSetMode (
UINT32 VramBaseAddress,
UINTN ModeNumber
)
{
// Make sure the interface clock is running
MmioWrite32 (CM_ICLKEN_DSS, EN_DSS);
// Stop the functional clocks
MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV));
// Program the DSS clock divisor
MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor));
// Start the functional clocks
MmioOr32 (CM_FCLKEN_DSS, (EN_DSS1 | EN_DSS2 | EN_TV));
// Wait for DSS to stabilize
gBS->Stall(1);
// Reset the subsystem
MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET);
while (!(MmioRead32 (DSS_SYSSTATUS) & DSS_RESETDONE));
// Configure LCD parameters
MmioWrite32 (DISPC_SIZE_LCD,
((LcdModes[ModeNumber].HorizontalResolution - 1)
| ((LcdModes[ModeNumber].VerticalResolution - 1) << 16))
);
MmioWrite32 (DISPC_TIMING_H,
( (LcdModes[ModeNumber].HSync - 1)
| ((LcdModes[ModeNumber].HFrontPorch - 1) << 8)
| ((LcdModes[ModeNumber].HBackPorch - 1) << 20))
);
MmioWrite32 (DISPC_TIMING_V,
( (LcdModes[ModeNumber].VSync - 1)
| ((LcdModes[ModeNumber].VFrontPorch - 1) << 8)
| ((LcdModes[ModeNumber].VBackPorch - 1) << 20))
);
// Set the framebuffer to only load frames (no gamma tables)
MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE);
MmioOr32 (DISPC_CONFIG, LOAD_FRAME_ONLY);
// Divisor for the pixel clock
MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) );
// Set up the graphics layer
MmioWrite32 (DISPC_GFX_PRELD, 0x2D8);
MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress);
MmioWrite32 (DISPC_GFX_SIZE,
((LcdModes[ModeNumber].HorizontalResolution - 1)
| ((LcdModes[ModeNumber].VerticalResolution - 1) << 16))
);
MmioWrite32(DISPC_GFX_ATTR, (GFXENABLE | RGB16 | BURSTSIZE16));
// Start it all
MmioOr32 (DISPC_CONTROL, (LCDENABLE | ACTIVEMATRIX | DATALINES24 | BYPASS_MODE | LCDENABLESIGNAL));
MmioOr32 (DISPC_CONTROL, GOLCD);
return EFI_SUCCESS;
}
EFI_STATUS
HwInitializeDisplay (
UINTN VramBaseAddress,
UINTN VramSize
)
{
EFI_STATUS Status;
UINT8 Data;
EFI_TPL OldTpl;
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
// Enable power lines used by TFP410
Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR (Status);
OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
Data = VAUX_DEV_GRP_P1;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEV_GRP), 1, &Data);
ASSERT_EFI_ERROR(Status);
Data = VAUX_DEDICATED_18V;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEDICATED), 1, &Data);
ASSERT_EFI_ERROR (Status);
// Power up TFP410 (set GPIO2 on TPS - for BeagleBoard-xM)
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data);
ASSERT_EFI_ERROR (Status);
Data |= BIT2;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data);
ASSERT_EFI_ERROR (Status);
Data = BIT2;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, SETGPIODATAOUT1), 1, &Data);
ASSERT_EFI_ERROR (Status);
gBS->RestoreTPL(OldTpl);
// Power up TFP410 (set GPIO 170 - for older BeagleBoards)
MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10);
MmioOr32 (GPIO6_BASE + GPIO_SETDATAOUT, BIT10);
return EFI_SUCCESS;
}
EFI_STATUS
InitializeDisplay (
IN LCD_INSTANCE* Instance
)
{
EFI_STATUS Status;
UINTN VramSize;
EFI_PHYSICAL_ADDRESS VramBaseAddress;
Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize);
if (EFI_ERROR (Status)) {
return Status;
}
Instance->Mode.FrameBufferBase = VramBaseAddress;
Instance->Mode.FrameBufferSize = VramSize;
Status = HwInitializeDisplay((UINTN)VramBaseAddress, VramSize);
if (!EFI_ERROR (Status)) {
mDisplayInitialized = TRUE;
}
return Status;
}
EFI_STATUS
EFIAPI
LcdGraphicsQueryMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
)
{
LCD_INSTANCE *Instance;
Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
if (!mDisplayInitialized) {
InitializeDisplay (Instance);
}
// Error checking
if ( (This == NULL) || (Info == NULL) || (SizeOfInfo == NULL) || (ModeNumber >= This->Mode->MaxMode) ) {
DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber ));
return EFI_INVALID_PARAMETER;
}
*Info = AllocateCopyPool(sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), &Instance->ModeInfo);
if (*Info == NULL) {
return EFI_OUT_OF_RESOURCES;
}
*SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);
(*Info)->Version = 0;
(*Info)->HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution;
(*Info)->VerticalResolution = LcdModes[ModeNumber].VerticalResolution;
(*Info)->PixelFormat = PixelBltOnly;
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
LcdGraphicsSetMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber
)
{
LCD_INSTANCE *Instance;
Instance = LCD_INSTANCE_FROM_GOP_THIS(This);
if (ModeNumber >= Instance->Mode.MaxMode) {
return EFI_UNSUPPORTED;
}
if (!mDisplayInitialized) {
InitializeDisplay (Instance);
}
DssSetMode((UINT32)Instance->Mode.FrameBufferBase, ModeNumber);
Instance->Mode.Mode = ModeNumber;
Instance->ModeInfo.HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution;
Instance->ModeInfo.VerticalResolution = LcdModes[ModeNumber].VerticalResolution;
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
LcdGraphicsOutputDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status = EFI_SUCCESS;
LCD_INSTANCE* Instance;
Status = LcdInstanceContructor (&Instance);
if (EFI_ERROR(Status)) {
goto EXIT;
}
// Install the Graphics Output Protocol and the Device Path
Status = gBS->InstallMultipleProtocolInterfaces(
&Instance->Handle,
&gEfiGraphicsOutputProtocolGuid, &Instance->Gop,
&gEfiDevicePathProtocolGuid, &Instance->DevicePath,
NULL
);
if (EFI_ERROR(Status)) {
DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the protocol. Exit Status=%r\n", Status));
goto EXIT;
}
// Register for an ExitBootServicesEvent
// When ExitBootServices starts, this function here will make sure that the graphics driver will shut down properly,
// i.e. it will free up all allocated memory and perform any necessary hardware re-configuration.
/*Status = gBS->CreateEvent (
EVT_SIGNAL_EXIT_BOOT_SERVICES,
TPL_NOTIFY,
LcdGraphicsExitBootServicesEvent, NULL,
&Instance->ExitBootServicesEvent
);
if (EFI_ERROR(Status)) {
DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the ExitBootServicesEvent handler. Exit Status=%r\n", Status));
goto EXIT_ERROR_UNINSTALL_PROTOCOL;
}*/
// To get here, everything must be fine, so just exit
goto EXIT;
//EXIT_ERROR_UNINSTALL_PROTOCOL:
/* The following function could return an error message,
* however, to get here something must have gone wrong already,
* so preserve the original error, i.e. don't change
* the Status variable, even it fails to uninstall the protocol.
*/
/* gBS->UninstallMultipleProtocolInterfaces (
Instance->Handle,
&gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics Output protocol
&gEfiDevicePathProtocolGuid, &Instance->DevicePath, // Uninstall device path
NULL
);*/
EXIT:
return Status;
}

151
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h
View File

@@ -1,151 +0,0 @@
/** @file
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __OMAP3_DSS_GRAPHICS__
#define __OMAP3_DSS_GRAPHICS__
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <Protocol/DevicePathToText.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/Cpu.h>
#include <Guid/GlobalVariable.h>
#include <Omap3530/Omap3530.h>
#include <TPS65950.h>
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} LCD_GRAPHICS_DEVICE_PATH;
typedef struct {
UINTN Signature;
EFI_HANDLE Handle;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode;
EFI_GRAPHICS_OUTPUT_PROTOCOL Gop;
LCD_GRAPHICS_DEVICE_PATH DevicePath;
// EFI_EVENT ExitBootServicesEvent;
} LCD_INSTANCE;
#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0')
#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE)
typedef struct {
UINTN Mode;
UINTN HorizontalResolution;
UINTN VerticalResolution;
UINT32 DssDivisor;
UINT32 DispcDivisor;
UINT32 HSync;
UINT32 HFrontPorch;
UINT32 HBackPorch;
UINT32 VSync;
UINT32 VFrontPorch;
UINT32 VBackPorch;
} LCD_MODE;
EFI_STATUS
InitializeDisplay (
IN LCD_INSTANCE* Instance
);
EFI_STATUS
EFIAPI
LcdGraphicsQueryMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
);
EFI_STATUS
EFIAPI
LcdGraphicsSetMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber
);
EFI_STATUS
EFIAPI
LcdGraphicsBlt (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer
);
// HW registers
#define CM_FCLKEN_DSS 0x48004E00
#define CM_ICLKEN_DSS 0x48004E10
#define DSS_CONTROL 0x48050040
#define DSS_SYSCONFIG 0x48050010
#define DSS_SYSSTATUS 0x48050014
#define DISPC_CONTROL 0x48050440
#define DISPC_CONFIG 0x48050444
#define DISPC_SIZE_LCD 0x4805047C
#define DISPC_TIMING_H 0x48050464
#define DISPC_TIMING_V 0x48050468
#define CM_CLKSEL_DSS 0x48004E40
#define DISPC_DIVISOR 0x48050470
#define DISPC_POL_FREQ 0x4805046C
#define DISPC_GFX_TABLE_BA 0x480504B8
#define DISPC_GFX_BA0 0x48050480
#define DISPC_GFX_BA1 0x48050484
#define DISPC_GFX_POS 0x48050488
#define DISPC_GFX_SIZE 0x4805048C
#define DISPC_GFX_ATTR 0x480504A0
#define DISPC_GFX_PRELD 0x4805062C
#define DISPC_DEFAULT_COLOR_0 0x4805044C
//#define DISPC_IRQSTATUS
// Bits
#define EN_TV 0x4
#define EN_DSS2 0x2
#define EN_DSS1 0x1
#define EN_DSS 0x1
#define DSS_SOFTRESET 0x2
#define DSS_RESETDONE 0x1
#define BYPASS_MODE (BIT15 | BIT16)
#define LCDENABLE BIT0
#define ACTIVEMATRIX BIT3
#define GOLCD BIT5
#define DATALINES24 (BIT8 | BIT9)
#define LCDENABLESIGNAL BIT28
#define GFXENABLE BIT0
#define RGB16 (0x6 << 1)
#define BURSTSIZE16 (0x2 << 6)
#define CLEARLOADMODE ~(BIT2 | BIT1)
#define LOAD_FRAME_ONLY BIT2
#endif

46
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
View File

@@ -1,46 +0,0 @@
#/** @file
#
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = LcdGraphicsDxe
FILE_GUID = E68088EF-D1A4-4336-C1DB-4D3A204730A6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = LcdGraphicsOutputDxeInitialize
[Sources.common]
LcdGraphicsOutputDxe.c
LcdGraphicsOutputBlt.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
ArmLib
UefiLib
BaseLib
DebugLib
TimerLib
UefiDriverEntryPoint
UefiBootServicesTableLib
IoLib
BaseMemoryLib
[Protocols]
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
gEfiDevicePathToTextProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Depex]
gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid

159
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
View File

@@ -1,159 +0,0 @@
/** @file
Debug Agent timer lib for OMAP 35xx.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <Omap3530/Omap3530.h>
volatile UINT32 gVector;
// Cached registers
volatile UINT32 gTISR;
volatile UINT32 gTCLR;
volatile UINT32 gTLDR;
volatile UINT32 gTCRR;
volatile UINT32 gTIER;
VOID
EnableInterruptSource (
VOID
)
{
UINTN Bank;
UINTN Bit;
// Map vector to FIQ, IRQ is default
MmioWrite32 (INTCPS_ILR (gVector), 1);
Bank = gVector / 32;
Bit = 1UL << (gVector % 32);
MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
}
VOID
DisableInterruptSource (
VOID
)
{
UINTN Bank;
UINTN Bit;
Bank = gVector / 32;
Bit = 1UL << (gVector % 32);
MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
}
/**
Setup all the hardware needed for the debug agents timer.
This function is used to set up debug enviroment. It may enable interrupts.
**/
VOID
EFIAPI
DebugAgentTimerIntialize (
VOID
)
{
UINT32 TimerBaseAddress;
UINT32 TimerNumber;
TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);
gVector = InterruptVectorForTimer (TimerNumber);
// Set up the timer registers
TimerBaseAddress = TimerBase (TimerNumber);
gTISR = TimerBaseAddress + GPTIMER_TISR;
gTCLR = TimerBaseAddress + GPTIMER_TCLR;
gTLDR = TimerBaseAddress + GPTIMER_TLDR;
gTCRR = TimerBaseAddress + GPTIMER_TCRR;
gTIER = TimerBaseAddress + GPTIMER_TIER;
if ((TimerNumber < 2) || (TimerNumber > 9)) {
// This code assumes one the General Purpose timers is used
// GPT2 - GPT9
CpuDeadLoop ();
}
// Set source clock for GPT2 - GPT9 to SYS_CLK
MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
}
/**
Set the period for the debug agent timer. Zero means disable the timer.
@param[in] TimerPeriodMilliseconds Frequency of the debug agent timer.
**/
VOID
EFIAPI
DebugAgentTimerSetPeriod (
IN UINT32 TimerPeriodMilliseconds
)
{
UINT64 TimerCount;
INT32 LoadValue;
if (TimerPeriodMilliseconds == 0) {
// Turn off GPTIMER3
MmioWrite32 (gTCLR, TCLR_ST_OFF);
DisableInterruptSource ();
} else {
// Calculate required timer count
TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));
// Set GPTIMER5 Load register
LoadValue = (INT32) -TimerCount;
MmioWrite32 (gTLDR, LoadValue);
MmioWrite32 (gTCRR, LoadValue);
// Enable Overflow interrupt
MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
EnableInterruptSource ();
}
}
/**
Perform End Of Interrupt for the debug agent timer. This is called in the
interrupt handler after the interrupt has been processed.
**/
VOID
EFIAPI
DebugAgentTimerEndOfInterrupt (
VOID
)
{
// Clear all timer interrupts
MmioWrite32 (gTISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
ArmDataSynchronizationBarrier ();
}

42
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
View File

@@ -1,42 +0,0 @@
#/** @file
# Component description file for Base PCI Cf8 Library.
#
# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
# Layers on top of an I/O Library instance.
# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DebugAgentTimerLibNull
FILE_GUID = E82F99DE-74ED-4e56-BBA1-B143FCA3F69A
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE
[Sources.common]
DebugAgentTimerLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
IoLib
OmapLib
ArmLib
[Pcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer
gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress

96
Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.c
View File

@@ -1,96 +0,0 @@
/** @file
Basic serial IO abstaction for GDB
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/GdbSerialLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
RETURN_STATUS
EFIAPI
GdbSerialLibConstructor (
VOID
)
{
return RETURN_SUCCESS;
}
RETURN_STATUS
EFIAPI
GdbSerialInit (
IN UINT64 BaudRate,
IN UINT8 Parity,
IN UINT8 DataBits,
IN UINT8 StopBits
)
{
return RETURN_SUCCESS;
}
BOOLEAN
EFIAPI
GdbIsCharAvailable (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE;
} else {
return FALSE;
}
}
CHAR8
EFIAPI
GdbGetChar (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
CHAR8 Char;
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
Char = MmioRead8(RBR);
return Char;
}
VOID
EFIAPI
GdbPutChar (
IN CHAR8 Char
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
MmioWrite8(THR, Char);
}
VOID
GdbPutString (
IN CHAR8 *String
)
{
while (*String != '\0') {
GdbPutChar (*String);
String++;
}
}

35
Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.inf
View File

@@ -1,35 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = GdbSerialLib
FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = GdbSerialLib
CONSTRUCTOR = GdbSerialLibConstructor
[Sources.common]
GdbSerialLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
DebugLib
IoLib
OmapLib
[FixedPcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart

40
Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
View File

@@ -1,40 +0,0 @@
#/** @file
# Timer library implementation
#
# A non-functional instance of the Timer Library that can be used as a template
# for the implementation of a functional timer library instance. This library instance can
# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer
# services as well as EBC modules that require timer services
# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardTimerLib
FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib
[Sources.common]
TimerLib.c
[Packages]
Omap35xxPkg/Omap35xxPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
DebugLib
OmapLib
IoLib
[Pcd]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds
gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer

151
Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c
View File

@@ -1,151 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
RETURN_STATUS
EFIAPI
TimerConstructor (
VOID
)
{
UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);
UINT32 TimerBaseAddress = TimerBase(Timer);
if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
// Set source clock for GPT3 & GPT4 to SYS_CLK
MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
// Set count & reload registers
MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
// Disable interrupts
MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
// Start Timer
MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
// Disable OMAP Watchdog timer (WDT2)
MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
}
return EFI_SUCCESS;
}
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
UINT64 NanoSeconds;
NanoSeconds = MultU64x32(MicroSeconds, 1000);
while (NanoSeconds > (UINTN)-1) {
NanoSecondDelay((UINTN)-1);
NanoSeconds -= (UINTN)-1;
}
NanoSecondDelay(NanoSeconds);
return MicroSeconds;
}
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
UINT32 Delay;
UINT32 StartTime;
UINT32 CurrentTime;
UINT32 ElapsedTime;
UINT32 TimerCountRegister;
Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1;
TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;
StartTime = MmioRead32 (TimerCountRegister);
do
{
CurrentTime = MmioRead32 (TimerCountRegister);
ElapsedTime = CurrentTime - StartTime;
} while (ElapsedTime < Delay);
NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds);
return NanoSeconds;
}
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
}
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts with the reload value
*StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);
}
if (EndValue != NULL) {
// Timer counts up to 0xFFFFFFFF
*EndValue = 0xFFFFFFFF;
}
return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz);
}
/**
Converts elapsed ticks of performance counter to time in nanoseconds.
This function converts the elapsed ticks of running performance counter to
time value in unit of nanoseconds.
@param Ticks The number of elapsed ticks of running performance counter.
@return The elapsed time in nanoseconds.
**/
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
)
{
UINT32 Period;
Period = PcdGet32 (PcdEmbeddedPerformanceCounterPeriodInNanoseconds);
return (Ticks * Period);
}

170
Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c
View File

@@ -1,170 +0,0 @@
/** @file
Abstractions for simple OMAP DMA channel.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/OmapDmaLib.h>
#include <Library/IoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Omap3530/Omap3530.h>
/**
Configure OMAP DMA Channel
@param Channel DMA Channel to configure
@param Dma4 Pointer to structure used to initialize DMA registers for the Channel
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
EnableDmaChannel (
IN UINTN Channel,
IN OMAP_DMA4 *DMA4
)
{
UINT32 RegVal;
if (Channel > DMA4_MAX_CHANNEL) {
return EFI_INVALID_PARAMETER;
}
/* 1) Configure the transfer parameters in the logical DMA registers */
/*-------------------------------------------------------------------*/
/* a) Set the data type CSDP[1:0], the Read/Write Port access type
CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
// Read CSDP
RegVal = MmioRead32 (DMA4_CSDP (Channel));
// Build reg
RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
// Write CSDP
MmioWrite32 (DMA4_CSDP (Channel), RegVal);
/* b) Set the number of element per frame CEN[23:0]*/
MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
/* c) Set the number of frame per block CFN[15:0]*/
MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
/* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
read/write priority CCR[6]/CCR[26]
I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
*/
// Read CCR
RegVal = MmioRead32 (DMA4_CCR (Channel));
// Build reg
RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber);
RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));
RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));
RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6));
RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));
// Write CCR
MmioWrite32 (DMA4_CCR (Channel), RegVal);
/* f)- Set the source element index CSEI[15:0]*/
MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
/* - Set the source frame index CSFI[15:0]*/
MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
/* - Set the destination element index CDEI[15:0]*/
MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
/* - Set the destination frame index CDFI[31:0]*/
MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
// Enable all the status bits since we are polling
MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);
MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
/*--------------------------------------------------------------*/
//write enable bit
MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
return EFI_SUCCESS;
}
/**
Turn of DMA channel configured by EnableDma().
@param Channel DMA Channel to configure
@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
@retval EFI_SUCCESS DMA hardware disabled
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
DisableDmaChannel (
IN UINTN Channel,
IN UINT32 SuccessMask,
IN UINT32 ErrorMask
)
{
EFI_STATUS Status = EFI_SUCCESS;
UINT32 Reg;
if (Channel > DMA4_MAX_CHANNEL) {
return EFI_INVALID_PARAMETER;
}
do {
Reg = MmioRead32 (DMA4_CSR(Channel));
if ((Reg & ErrorMask) != 0) {
Status = EFI_DEVICE_ERROR;
DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
break;
}
} while ((Reg & SuccessMask) != SuccessMask);
// Disable all status bits and clear them
MmioWrite32 (DMA4_CICR (Channel), 0);
MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
return Status;
}

43
Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf
View File

@@ -1,43 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = OmapDmaLib
FILE_GUID = 09B17D99-BB07-49a8-B0D2-06D6AFCBE3AB
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = OmapDmaLib
[Sources.common]
OmapDmaLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
DebugLib
UefiBootServicesTableLib
MemoryAllocationLib
IoLib
BaseMemoryLib
ArmLib
[Protocols]
gEfiCpuArchProtocolGuid
[Guids]
[Pcd]
[Depex]
gEfiCpuArchProtocolGuid

77
Omap35xxPkg/Library/OmapLib/OmapLib.c
View File

@@ -1,77 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
UINT32
GpioBase (
IN UINTN Port
)
{
switch (Port) {
case 1: return GPIO1_BASE;
case 2: return GPIO2_BASE;
case 3: return GPIO3_BASE;
case 4: return GPIO4_BASE;
case 5: return GPIO5_BASE;
case 6: return GPIO6_BASE;
default: ASSERT(FALSE); return 0;
}
}
UINT32
TimerBase (
IN UINTN Timer
)
{
switch (Timer) {
case 1: return GPTIMER1_BASE;
case 2: return GPTIMER2_BASE;
case 3: return GPTIMER3_BASE;
case 4: return GPTIMER4_BASE;
case 5: return GPTIMER5_BASE;
case 6: return GPTIMER6_BASE;
case 7: return GPTIMER7_BASE;
case 8: return GPTIMER8_BASE;
case 9: return GPTIMER9_BASE;
case 10: return GPTIMER10_BASE;
case 11: return GPTIMER11_BASE;
case 12: return GPTIMER12_BASE;
default: return 0;
}
}
UINTN
InterruptVectorForTimer (
IN UINTN Timer
)
{
if ((Timer < 1) || (Timer > 12)) {
ASSERT(FALSE);
return 0xFFFFFFFF;
}
return 36 + Timer;
}
UINT32
UartBase (
IN UINTN Uart
)
{
switch (Uart) {
case 1: return UART1_BASE;
case 2: return UART2_BASE;
case 3: return UART3_BASE;
default: ASSERT(FALSE); return 0;
}
}

31
Omap35xxPkg/Library/OmapLib/OmapLib.inf
View File

@@ -1,31 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = OmapLib
FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = OmapLib
[Sources.common]
OmapLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
DebugLib
[Protocols]
[Guids]
[Pcd]

291
Omap35xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c
View File

@@ -1,291 +0,0 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Protocol/RealTimeClock.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Omap3530/Omap3530.h>
#include <TPS65950.h>
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
INT16 TimeZone = EFI_UNSPECIFIED_TIMEZONE;
/**
Returns the current time and date information, and the time-keeping capabilities
of the hardware platform.
@param Time A pointer to storage to receive a snapshot of the current time.
@param Capabilities An optional pointer to a buffer to receive the real time clock
device's capabilities.
@retval EFI_SUCCESS The operation completed successfully.
@retval EFI_INVALID_PARAMETER Time is NULL.
@retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
**/
EFI_STATUS
EFIAPI
LibGetTime (
OUT EFI_TIME *Time,
OUT EFI_TIME_CAPABILITIES *Capabilities
)
{
EFI_STATUS Status;
UINT8 Data;
EFI_TPL OldTpl;
if (Time == NULL) {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
/* Get time and date */
ZeroMem(Time, sizeof(EFI_TIME));
// Latch values
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data |= BIT6;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
// Read registers
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Year = 2000 + ((Data >> 4) & 0xF) * 10 + (Data & 0xF);
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Month = ((Data >> 4) & 0x1) * 10 + (Data & 0xF);
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Day = ((Data >> 4) & 0x3) * 10 + (Data & 0xF);
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Hour = ((Data >> 4) & 0x3) * 10 + (Data & 0xF);
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Minute = ((Data >> 4) & 0x7) * 10 + (Data & 0xF);
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Time->Second = ((Data >> 4) & 0x7) * 10 + (Data & 0xF);
Time->TimeZone = TimeZone;
// TODO: check what to use here
Time->Daylight = EFI_TIME_ADJUST_DAYLIGHT;
// Set capabilities
// TODO: Set real capabilities
if (Capabilities != NULL) {
Capabilities->Resolution = 1;
Capabilities->Accuracy = 50000000;
Capabilities->SetsToZero = FALSE;
}
EXIT:
gBS->RestoreTPL(OldTpl);
return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR;
}
/**
Sets the current local time and date information.
@param Time A pointer to the current time.
@retval EFI_SUCCESS The operation completed successfully.
@retval EFI_INVALID_PARAMETER A time field is out of range.
@retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
**/
EFI_STATUS
EFIAPI
LibSetTime (
IN EFI_TIME *Time
)
{
EFI_STATUS Status;
UINT8 Data;
UINT8 MonthDayCount[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
EFI_TPL OldTpl;
// Input validation according both to UEFI spec and hardware constraints
// UEFI spec says valid year range is 1900-9999 but TPS only supports 2000-2099
if ( (Time == NULL)
|| (Time->Year < 2000 || Time->Year > 2099)
|| (Time->Month < 1 || Time->Month > 12)
|| (Time->Day < 1 || Time->Day > MonthDayCount[Time->Month])
|| (Time->Hour > 23)
|| (Time->Minute > 59)
|| (Time->Second > 59)
|| (Time->Nanosecond > 999999999)
|| ((Time->TimeZone < -1440 || Time->TimeZone > 1440) && Time->TimeZone != 2047)
) {
return EFI_INVALID_PARAMETER;
}
OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
Data = Time->Year - 2000;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data = ((Time->Month / 10) << 4) | (Time->Month % 10);
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data = ((Time->Day / 10) << 4) | (Time->Day % 10);
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data = ((Time->Hour / 10) << 4) | (Time->Hour % 10);
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data = ((Time->Minute / 10) << 4) | (Time->Minute % 10);
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
Data = ((Time->Second / 10) << 4) | (Time->Second % 10);
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data);
if (Status != EFI_SUCCESS) goto EXIT;
TimeZone = Time->TimeZone;
EXIT:
gBS->RestoreTPL(OldTpl);
return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR;
}
/**
Returns the current wakeup alarm clock setting.
@param Enabled Indicates if the alarm is currently enabled or disabled.
@param Pending Indicates if the alarm signal is pending and requires acknowledgement.
@param Time The current alarm setting.
@retval EFI_SUCCESS The alarm settings were returned.
@retval EFI_INVALID_PARAMETER Any parameter is NULL.
@retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
**/
EFI_STATUS
EFIAPI
LibGetWakeupTime (
OUT BOOLEAN *Enabled,
OUT BOOLEAN *Pending,
OUT EFI_TIME *Time
)
{
return EFI_UNSUPPORTED;
}
/**
Sets the system wakeup alarm clock time.
@param Enabled Enable or disable the wakeup alarm.
@param Time If Enable is TRUE, the time to set the wakeup alarm for.
@retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
Enable is FALSE, then the wakeup alarm was disabled.
@retval EFI_INVALID_PARAMETER A time field is out of range.
@retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
@retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
**/
EFI_STATUS
EFIAPI
LibSetWakeupTime (
IN BOOLEAN Enabled,
OUT EFI_TIME *Time
)
{
return EFI_UNSUPPORTED;
}
/**
This is the declaration of an EFI image entry point. This can be the entry point to an application
written to this specification, an EFI boot service driver, or an EFI runtime driver.
@param ImageHandle Handle that identifies the loaded image.
@param SystemTable System Table for this image.
@retval EFI_SUCCESS The operation completed successfully.
**/
EFI_STATUS
EFIAPI
LibRtcInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
UINT8 Data;
EFI_TPL OldTpl;
Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status);
OldTpl = gBS->RaiseTPL(TPL_NOTIFY);
Data = 1;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data);
ASSERT_EFI_ERROR(Status);
gBS->RestoreTPL(OldTpl);
// Setup the setters and getters
gRT->GetTime = LibGetTime;
gRT->SetTime = LibSetTime;
gRT->GetWakeupTime = LibGetWakeupTime;
gRT->SetWakeupTime = LibSetWakeupTime;
// Install the protocol
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiRealTimeClockArchProtocolGuid, NULL,
NULL
);
return Status;
}
/**
Fixup internal data so that EFI can be call in virtual mode.
Call the passed in Child Notify event and convert any pointers in
lib to virtual mode.
@param[in] Event The Event that is being processed
@param[in] Context Event Context
**/
VOID
EFIAPI
LibRtcVirtualNotifyEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
return;
}

32
Omap35xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf
View File

@@ -1,32 +0,0 @@
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = RealTimeClockLib
FILE_GUID = EC1713DB-7DB5-4c99-8FE2-6F52F95A1132
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RealTimeClockLib
[Sources.common]
RealTimeClockLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
IoLib
UefiLib
DebugLib
PcdLib
[Protocols]
gEmbeddedExternalDeviceProtocolGuid
[depex]
gEmbeddedExternalDeviceProtocolGuid

208
Omap35xxPkg/Library/SerialPortLib/SerialPortLib.c
View File

@@ -1,208 +0,0 @@
/** @file
Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/SerialPortLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
/*
Programmed hardware of Serial port.
@return Always return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
SerialPortInitialize (
VOID
)
{
// assume assembly code at reset vector has setup UART
return RETURN_SUCCESS;
}
/**
Write data to serial device.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
**/
UINTN
EFIAPI
SerialPortWrite (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
MmioWrite8(THR, *Buffer);
}
return NumberOfBytes;
}
/**
Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Aactual number of bytes read from serial device.
**/
UINTN
EFIAPI
SerialPortRead (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
*Buffer = MmioRead8(RBR);
}
return NumberOfBytes;
}
/**
Check to see if any data is avaiable to be read from the debug device.
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
@retval EFI_NOT_READY No data is avaiable to be read
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
**/
BOOLEAN
EFIAPI
SerialPortPoll (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE;
} else {
return FALSE;
}
}
/**
Sets the control bits on a serial device.
@param[in] Control Sets the bits of Control that are settable.
@retval RETURN_SUCCESS The new control bits were set on the serial device.
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
**/
RETURN_STATUS
EFIAPI
SerialPortSetControl (
IN UINT32 Control
)
{
return RETURN_UNSUPPORTED;
}
/**
Retrieve the status of the control bits on a serial device.
@param[out] Control A pointer to return the current control signals from the serial device.
@retval RETURN_SUCCESS The control bits were read from the serial device.
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
**/
RETURN_STATUS
EFIAPI
SerialPortGetControl (
OUT UINT32 *Control
)
{
*Control = 0;
if (!SerialPortPoll ()) {
*Control = EFI_SERIAL_INPUT_BUFFER_EMPTY;
}
return RETURN_SUCCESS;
}
/**
Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
data bits, and stop bits on a serial device.
@param BaudRate The requested baud rate. A BaudRate value of 0 will use the
device's default interface speed.
On output, the value actually set.
@param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
serial interface. A ReceiveFifoDepth value of 0 will use
the device's default FIFO depth.
On output, the value actually set.
@param Timeout The requested time out for a single character in microseconds.
This timeout applies to both the transmit and receive side of the
interface. A Timeout value of 0 will use the device's default time
out value.
On output, the value actually set.
@param Parity The type of parity to use on this serial device. A Parity value of
DefaultParity will use the device's default parity value.
On output, the value actually set.
@param DataBits The number of data bits to use on the serial device. A DataBits
vaule of 0 will use the device's default data bit setting.
On output, the value actually set.
@param StopBits The number of stop bits to use on this serial device. A StopBits
value of DefaultStopBits will use the device's default number of
stop bits.
On output, the value actually set.
@retval RETURN_SUCCESS The new attributes were set on the serial device.
@retval RETURN_UNSUPPORTED The serial device does not support this operation.
@retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
@retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
**/
RETURN_STATUS
EFIAPI
SerialPortSetAttributes (
IN OUT UINT64 *BaudRate,
IN OUT UINT32 *ReceiveFifoDepth,
IN OUT UINT32 *Timeout,
IN OUT EFI_PARITY_TYPE *Parity,
IN OUT UINT8 *DataBits,
IN OUT EFI_STOP_BITS_TYPE *StopBits
)
{
return RETURN_UNSUPPORTED;
}

40
Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf
View File

@@ -1,40 +0,0 @@
#/** @file
# EDK Serial port lib
#
# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardSerialPortLib
FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SerialPortLib
#
# VALID_ARCHITECTURES = ARM IA32 X64 EBC
#
[Sources.common]
SerialPortLib.c
[LibraryClasses]
DebugLib
IoLib
OmapLib
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[FixedPcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart

1492
Omap35xxPkg/MMCHSDxe/MMCHS.c
View File

File diff suppressed because it is too large Load Diff

169
Omap35xxPkg/MMCHSDxe/MMCHS.h
View File

@@ -1,169 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MMCHS_H_
#define _MMCHS_H_
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/OmapLib.h>
#include <Library/OmapDmaLib.h>
#include <Library/DmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/BlockIo.h>
#include <Protocol/DevicePath.h>
#include <Omap3530/Omap3530.h>
#include <TPS65950.h>
#define MAX_RETRY_COUNT (100*5)
#define HCS BIT30 //Host capacity support/1 = Supporting high capacity
#define CCS BIT30 //Card capacity status/1 = High capacity card
typedef struct {
UINT32 Reserved0: 7; // 0
UINT32 V170_V195: 1; // 1.70V - 1.95V
UINT32 V200_V260: 7; // 2.00V - 2.60V
UINT32 V270_V360: 9; // 2.70V - 3.60V
UINT32 RESERVED_1: 5; // Reserved
UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
}OCR;
typedef struct {
UINT32 NOT_USED; // 1 [0:0]
UINT32 CRC; // CRC7 checksum [7:1]
UINT32 MDT; // Manufacturing date [19:8]
UINT32 RESERVED_1; // Reserved [23:20]
UINT32 PSN; // Product serial number [55:24]
UINT8 PRV; // Product revision [63:56]
UINT8 PNM[5]; // Product name [64:103]
UINT16 OID; // OEM/Application ID [119:104]
UINT8 MID; // Manufacturer ID [127:120]
}CID;
typedef struct {
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 RESERVED_1: 2; // Reserved [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 RESERVED_2: 5; // Reserved [20:16]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 RESERVED_3: 2; // Reserved [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
UINT32 C_SIZELow2: 2; // Device size [63:62]
UINT32 C_SIZEHigh10: 10;// Device size [73:64]
UINT32 RESERVED_4: 2; // Reserved [75:74]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT32 CCC: 12;// Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 RESERVED_5: 6; // Reserved [125:120]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD;
typedef struct {
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 RESERVED_1: 2; // Reserved [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 RESERVED_2: 5; // Reserved [20:16]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 RESERVED_3: 2; // Reserved [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
UINT16 RESERVED_4: 1; // Reserved [47:47]
UINT32 C_SIZELow16: 16;// Device size [69:48]
UINT32 C_SIZEHigh6: 6; // Device size [69:48]
UINT32 RESERVED_5: 6; // Reserved [75:70]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT16 CCC: 12;// Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 RESERVED_6: 6; // 0 [125:120]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD_SDV2;
typedef enum {
UNKNOWN_CARD,
MMC_CARD, //MMC card
SD_CARD, //SD 1.1 card
SD_CARD_2, //SD 2.0 or above standard card
SD_CARD_2_HIGH //SD 2.0 or above high capacity card
} CARD_TYPE;
typedef enum {
READ,
WRITE
} OPERATION_TYPE;
typedef struct {
UINT16 RCA;
UINTN BlockSize;
UINTN NumBlocks;
UINTN ClockFrequencySelect;
CARD_TYPE CardType;
OCR OCRData;
CID CIDData;
CSD CSDData;
} CARD_INFO;
EFI_STATUS
DetectCard (
VOID
);
extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
#endif

48
Omap35xxPkg/MMCHSDxe/MMCHS.inf
View File

@@ -1,48 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = MMCHS
FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = MMCHSInitialize
[Sources.common]
MMCHS.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
OmapDmaLib
DmaLib
[Guids]
[Protocols]
gEfiBlockIoProtocolGuid
gEfiCpuArchProtocolGuid
gEfiDevicePathProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Pcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds
[depex]
gEmbeddedExternalDeviceProtocolGuid

671
Omap35xxPkg/MmcHostDxe/MmcHostDxe.c
View File

@@ -1,671 +0,0 @@
/** @file
*
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "MmcHostDxe.h"
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
UINT8 mMaxDataTransferRate = 0;
UINT32 mRca = 0;
BOOLEAN mBitModeSet = FALSE;
typedef struct {
VENDOR_DEVICE_PATH Mmc;
EFI_DEVICE_PATH End;
} MMCHS_DEVICE_PATH;
MMCHS_DEVICE_PATH gMMCDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
HW_VENDOR_DP,
{ (UINT8)(sizeof(VENDOR_DEVICE_PATH)), (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8) },
},
{ 0xb615f1f5, 0x5088, 0x43cd, { 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00 } }
},
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{ sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
}
};
BOOLEAN
IgnoreCommand (
UINT32 Command
)
{
switch(Command) {
case MMC_CMD12:
return TRUE;
case MMC_CMD13:
return TRUE;
default:
return FALSE;
}
}
UINT32
TranslateCommand (
UINT32 Command
)
{
UINT32 Translation;
switch(Command) {
case MMC_CMD2:
Translation = CMD2;
break;
case MMC_CMD3:
Translation = CMD3;
break;
/*case MMC_CMD6:
Translation = CMD6;
break;*/
case MMC_CMD7:
Translation = CMD7;
break;
case MMC_CMD8:
Translation = CMD8;
break;
case MMC_CMD9:
Translation = CMD9;
break;
/*case MMC_CMD12:
Translation = CMD12;
break;
case MMC_CMD13:
Translation = CMD13;
break;*/
case MMC_CMD16:
Translation = CMD16;
break;
case MMC_CMD17:
Translation = 0x113A0014;//CMD17;
break;
case MMC_CMD24:
Translation = CMD24 | 4;
break;
case MMC_CMD55:
Translation = CMD55;
break;
case MMC_ACMD41:
Translation = ACMD41;
break;
default:
Translation = Command;
}
return Translation;
}
VOID
CalculateCardCLKD (
UINTN *ClockFrequencySelect
)
{
UINTN TransferRateValue = 0;
UINTN TimeValue = 0 ;
UINTN Frequency = 0;
DEBUG ((DEBUG_BLKIO, "CalculateCardCLKD()\n"));
// For SD Cards we would need to send CMD6 to set
// speeds abouve 25MHz. High Speed mode 50 MHz and up
// Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED)
switch (mMaxDataTransferRate & 0x7) { // 2
case 0:
TransferRateValue = 100 * 1000;
break;
case 1:
TransferRateValue = 1 * 1000 * 1000;
break;
case 2:
TransferRateValue = 10 * 1000 * 1000;
break;
case 3:
TransferRateValue = 100 * 1000 * 1000;
break;
default:
DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n"));
ASSERT(FALSE);
return;
}
//Calculate Time value (Bits 6:3 of TRAN_SPEED)
switch ((mMaxDataTransferRate >> 3) & 0xF) { // 6
case 1:
TimeValue = 10;
break;
case 2:
TimeValue = 12;
break;
case 3:
TimeValue = 13;
break;
case 4:
TimeValue = 15;
break;
case 5:
TimeValue = 20;
break;
case 6:
TimeValue = 25;
break;
case 7:
TimeValue = 30;
break;
case 8:
TimeValue = 35;
break;
case 9:
TimeValue = 40;
break;
case 10:
TimeValue = 45;
break;
case 11:
TimeValue = 50;
break;
case 12:
TimeValue = 55;
break;
case 13:
TimeValue = 60;
break;
case 14:
TimeValue = 70;
break;
case 15:
TimeValue = 80;
break;
default:
DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n"));
ASSERT(FALSE);
return;
}
Frequency = TransferRateValue * TimeValue/10;
// Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
*ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1);
DEBUG ((DEBUG_BLKIO, "mMaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", mMaxDataTransferRate, Frequency/1000, *ClockFrequencySelect));
}
VOID
UpdateMMCHSClkFrequency (
UINTN NewCLKD
)
{
DEBUG ((DEBUG_BLKIO, "UpdateMMCHSClkFrequency()\n"));
// Set Clock enable to 0x0 to not provide the clock to the card
MmioAnd32 (MMCHS_SYSCTL, ~CEN);
// Set new clock frequency.
MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
// Poll till Internal Clock Stable
while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
// Set Clock enable to 0x1 to provide the clock to the card
MmioOr32 (MMCHS_SYSCTL, CEN);
}
EFI_STATUS
InitializeMMCHS (
VOID
)
{
UINT8 Data;
EFI_STATUS Status;
DEBUG ((DEBUG_BLKIO, "InitializeMMCHS()\n"));
// Select Device group to belong to P1 device group in Power IC.
Data = DEV_GRP_P1;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEV_GRP), 1, &Data);
ASSERT_EFI_ERROR(Status);
// Configure voltage regulator for MMC1 in Power IC to output 3.0 voltage.
Data = VSEL_3_00V;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEDICATED_REG), 1, &Data);
ASSERT_EFI_ERROR(Status);
// After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable.
MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
// Enable WP GPIO
MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
// Enable Card Detect
Data = CARD_DETECT_ENABLE;
gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, TPS65950_GPIO_CTRL), 1, &Data);
return Status;
}
BOOLEAN
MMCIsCardPresent (
IN EFI_MMC_HOST_PROTOCOL *This
)
{
EFI_STATUS Status;
UINT8 Data;
//
// Card detect is a GPIO0 on the TPS65950
//
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATAIN1), 1, &Data);
if (EFI_ERROR (Status)) {
return FALSE;
}
return !(Data & CARD_DETECT_BIT);
}
BOOLEAN
MMCIsReadOnly (
IN EFI_MMC_HOST_PROTOCOL *This
)
{
/* Note:
* On our BeagleBoard the SD card WP pin is always read as TRUE.
* Probably something wrong with GPIO configuration.
* BeagleBoard-xM uses microSD cards so there is no write protect at all.
* Hence commenting out SD card WP pin read status.
*/
//return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
return 0;
}
// TODO
EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;
EFI_STATUS
MMCBuildDevicePath (
IN EFI_MMC_HOST_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
)
{
EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));
CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);
*DevicePath = NewDevicePathNode;
return EFI_SUCCESS;
}
EFI_STATUS
MMCSendCommand (
IN EFI_MMC_HOST_PROTOCOL *This,
IN MMC_CMD MmcCmd,
IN UINT32 Argument
)
{
UINTN MmcStatus;
UINTN RetryCount = 0;
if (IgnoreCommand(MmcCmd))
return EFI_SUCCESS;
MmcCmd = TranslateCommand(MmcCmd);
//DEBUG ((EFI_D_ERROR, "MMCSendCommand(%d)\n", MmcCmd));
// Check if command line is in use or not. Poll till command line is available.
while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
// Provide the block size.
MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
// Setting Data timeout counter value to max value.
MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
// Clear Status register.
MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
// Set command argument register
MmioWrite32 (MMCHS_ARG, Argument);
//TODO: fix this
//Enable interrupt enable events to occur
//MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
// Send a command
MmioWrite32 (MMCHS_CMD, MmcCmd);
// Check for the command status.
while (RetryCount < MAX_RETRY_COUNT) {
do {
MmcStatus = MmioRead32 (MMCHS_STAT);
} while (MmcStatus == 0);
// Read status of command response
if ((MmcStatus & ERRI) != 0) {
// Perform soft-reset for mmci_cmd line.
MmioOr32 (MMCHS_SYSCTL, SRC);
while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
//DEBUG ((EFI_D_INFO, "MmcStatus: 0x%x\n", MmcStatus));
return EFI_DEVICE_ERROR;
}
// Check if command is completed.
if ((MmcStatus & CC) == CC) {
MmioWrite32 (MMCHS_STAT, CC);
break;
}
RetryCount++;
}
if (RetryCount == MAX_RETRY_COUNT) {
DEBUG ((DEBUG_BLKIO, "MMCSendCommand: Timeout\n"));
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
EFI_STATUS
MMCNotifyState (
IN EFI_MMC_HOST_PROTOCOL *This,
IN MMC_STATE State
)
{
EFI_STATUS Status;
UINTN FreqSel;
switch(State) {
case MmcInvalidState:
ASSERT(0);
break;
case MmcHwInitializationState:
mBitModeSet = FALSE;
DEBUG ((DEBUG_BLKIO, "MMCHwInitializationState()\n"));
Status = InitializeMMCHS ();
if (EFI_ERROR(Status)) {
DEBUG ((DEBUG_BLKIO, "Initialize MMC host controller fails. Status: %x\n", Status));
return Status;
}
// Software reset of the MMCHS host controller.
MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
gBS->Stall(1000);
while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
// Soft reset for all.
MmioWrite32 (MMCHS_SYSCTL, SRA);
gBS->Stall(1000);
while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
//Voltage capabilities initialization. Activate VS18 and VS30.
MmioOr32 (MMCHS_CAPA, (VS30 | VS18));
// Wakeup configuration
MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);
MmioOr32 (MMCHS_HCTL, IWE);
// MMCHS Controller default initialization
MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
// Enable internal clock
MmioOr32 (MMCHS_SYSCTL, ICE);
// Set the clock frequency to 80KHz.
UpdateMMCHSClkFrequency (CLKD_80KHZ);
// Enable SD bus power.
MmioOr32 (MMCHS_HCTL, (SDBP_ON));
// Poll till SD bus power bit is set.
while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
// Enable interrupts.
MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
// Controller INIT procedure start.
MmioOr32 (MMCHS_CON, INIT);
MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32 (MMCHS_STAT) & CC));
// Wait for 1 ms
gBS->Stall (1000);
// Set CC bit to 0x1 to clear the flag
MmioOr32 (MMCHS_STAT, CC);
// Retry INIT procedure.
MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32 (MMCHS_STAT) & CC));
// End initialization sequence
MmioAnd32 (MMCHS_CON, ~INIT);
MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));
// Change clock frequency to 400KHz to fit protocol
UpdateMMCHSClkFrequency(CLKD_400KHZ);
MmioOr32 (MMCHS_CON, OD);
break;
case MmcIdleState:
break;
case MmcReadyState:
break;
case MmcIdentificationState:
break;
case MmcStandByState:
CalculateCardCLKD (&FreqSel);
UpdateMMCHSClkFrequency (FreqSel);
break;
case MmcTransferState:
if (!mBitModeSet) {
Status = MMCSendCommand (This, CMD55, mRca << 16);
if (!EFI_ERROR (Status)) {
// Set device into 4-bit data bus mode
Status = MMCSendCommand (This, ACMD6, 0x2);
if (!EFI_ERROR (Status)) {
// Set host controler into 4-bit mode
MmioOr32 (MMCHS_HCTL, DTW_4_BIT);
DEBUG ((DEBUG_BLKIO, "SD Memory Card set to 4-bit mode\n"));
mBitModeSet = TRUE;
}
}
}
break;
case MmcSendingDataState:
break;
case MmcReceiveDataState:
break;
case MmcProgrammingState:
break;
case MmcDisconnectState:
default:
ASSERT(0);
}
return EFI_SUCCESS;
}
EFI_STATUS
MMCReceiveResponse (
IN EFI_MMC_HOST_PROTOCOL *This,
IN MMC_RESPONSE_TYPE Type,
IN UINT32* Buffer
)
{
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
if (Type == MMC_RESPONSE_TYPE_R2) {
Buffer[0] = MmioRead32 (MMCHS_RSP10);
Buffer[1] = MmioRead32 (MMCHS_RSP32);
Buffer[2] = MmioRead32 (MMCHS_RSP54);
Buffer[3] = MmioRead32 (MMCHS_RSP76);
} else {
Buffer[0] = MmioRead32 (MMCHS_RSP10);
}
if (Type == MMC_RESPONSE_TYPE_CSD) {
mMaxDataTransferRate = Buffer[3] & 0xFF;
} else if (Type == MMC_RESPONSE_TYPE_RCA) {
mRca = Buffer[0] >> 16;
}
return EFI_SUCCESS;
}
EFI_STATUS
MMCReadBlockData (
IN EFI_MMC_HOST_PROTOCOL *This,
IN EFI_LBA Lba,
IN UINTN Length,
IN UINT32* Buffer
)
{
UINTN MmcStatus;
UINTN Count;
UINTN RetryCount = 0;
DEBUG ((DEBUG_BLKIO, "MMCReadBlockData(LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n", Lba, Length, Buffer));
// Check controller status to make sure there is no error.
while (RetryCount < MAX_RETRY_COUNT) {
do {
// Read Status.
MmcStatus = MmioRead32 (MMCHS_STAT);
} while(MmcStatus == 0);
// Check if Buffer read ready (BRR) bit is set?
if (MmcStatus & BRR) {
// Clear BRR bit
MmioOr32 (MMCHS_STAT, BRR);
for (Count = 0; Count < Length / 4; Count++) {
*Buffer++ = MmioRead32(MMCHS_DATA);
}
break;
}
RetryCount++;
}
if (RetryCount == MAX_RETRY_COUNT) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
EFI_STATUS
MMCWriteBlockData (
IN EFI_MMC_HOST_PROTOCOL *This,
IN EFI_LBA Lba,
IN UINTN Length,
IN UINT32* Buffer
)
{
UINTN MmcStatus;
UINTN Count;
UINTN RetryCount = 0;
// Check controller status to make sure there is no error.
while (RetryCount < MAX_RETRY_COUNT) {
do {
// Read Status.
MmcStatus = MmioRead32 (MMCHS_STAT);
} while(MmcStatus == 0);
// Check if Buffer write ready (BWR) bit is set?
if (MmcStatus & BWR) {
// Clear BWR bit
MmioOr32 (MMCHS_STAT, BWR);
// Write block worth of data.
for (Count = 0; Count < Length / 4; Count++) {
MmioWrite32 (MMCHS_DATA, *Buffer++);
}
break;
}
RetryCount++;
}
if (RetryCount == MAX_RETRY_COUNT) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
EFI_MMC_HOST_PROTOCOL gMMCHost = {
MMC_HOST_PROTOCOL_REVISION,
MMCIsCardPresent,
MMCIsReadOnly,
MMCBuildDevicePath,
MMCNotifyState,
MMCSendCommand,
MMCReceiveResponse,
MMCReadBlockData,
MMCWriteBlockData
};
EFI_STATUS
MMCInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle = NULL;
DEBUG ((DEBUG_BLKIO, "MMCInitialize()\n"));
Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status);
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiMmcHostProtocolGuid, &gMMCHost,
NULL
);
ASSERT_EFI_ERROR (Status);
return Status;
}

38
Omap35xxPkg/MmcHostDxe/MmcHostDxe.h
View File

@@ -1,38 +0,0 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef _MMC_HOST_DXE_H_
#define _MMC_HOST_DXE_H_
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/OmapLib.h>
#include <Library/OmapDmaLib.h>
#include <Library/DmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/BlockIo.h>
#include <Protocol/DevicePath.h>
#include <Protocol/MmcHost.h>
#include <Omap3530/Omap3530.h>
#include <TPS65950.h>
#define MAX_RETRY_COUNT (100*5)
extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
#endif

47
Omap35xxPkg/MmcHostDxe/MmcHostDxe.inf
View File

@@ -1,47 +0,0 @@
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = MMC
FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = MMCInitialize
[Sources.common]
MmcHostDxe.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
OmapDmaLib
DmaLib
[Guids]
[Protocols]
gEfiBlockIoProtocolGuid
gEfiCpuArchProtocolGuid
gEfiDevicePathProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
gEfiMmcHostProtocolGuid
[Pcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds
[depex]
gEmbeddedExternalDeviceProtocolGuid

52
Omap35xxPkg/Omap35xxPkg.dec
View File

@@ -1,52 +0,0 @@
#/** @file
# Omap35xx SoC package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = Omap35xxPkg
PACKAGE_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[LibraryClasses]
## @libraryclass Abstract location of basic OMAP components
##
OmapLib|Include/Library/OmapLib.h
## @libraryclass Abstract OMAP and ARM DMA, modeled after PCI IO protocol
##
OmapDmaLib|Include/Library/OmapDmaLib.h
[Guids.common]
gOmap35xxTokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} }
[PcdsFeatureFlag.common]
[PcdsFixedAtBuild.common]
gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3|UINT32|0x00000202
gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x00000000|UINT32|0x00000203
gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x00000000|UINT32|0x00000204
gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3|UINT32|0x00000205
gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4|UINT32|0x00000206
gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer|5|UINT32|0x00000207
gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|77|UINT32|0x00000208
gOmap35xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds|1000000|UINT32|0x00000209

183
Omap35xxPkg/Omap35xxPkg.dsc
View File

@@ -1,183 +0,0 @@
#/** @file
# Omap35xx SoC package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = Omap35xxPkg
PLATFORM_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Omap35xxPkg
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
DEFINE TARGET_HACK = DEBUG
[LibraryClasses.common]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
OmapLib|Omap35xxPkg/Library/OmapLib/OmapLib.inf
OmapDmaLib|Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
TimerLib|Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
#
# Assume everything is fixed at build
#
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
[LibraryClasses.common.DXE_DRIVER]
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
[LibraryClasses.ARM]
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
[BuildOptions]
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb
GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a
RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu 7-A
RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu 7-A
*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFixedAtBuild.common]
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED 0x02
# DEBUG_CODE_ENABLED 0x04
# CLEAR_MEMORY_ENABLED 0x08
# ASSERT_BREAKPOINT_ENABLED 0x10
# ASSERT_DEADLOOP_ENABLED 0x20
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
# DEBUG_INIT 0x00000001 // Initialization
# DEBUG_WARN 0x00000002 // Warnings
# DEBUG_LOAD 0x00000004 // Load events
# DEBUG_FS 0x00000008 // EFI File system
# DEBUG_POOL 0x00000010 // Alloc & Free (pool)
# DEBUG_PAGE 0x00000020 // Alloc & Free (page)
# DEBUG_INFO 0x00000040 // Informational debug messages
# DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
# DEBUG_VARIABLE 0x00000100 // Variable
# DEBUG_BM 0x00000400 // Boot Manager
# DEBUG_BLKIO 0x00001000 // BlkIo Driver
# DEBUG_NET 0x00004000 // SNP Driver
# DEBUG_UNDI 0x00010000 // UNDI Driver
# DEBUG_LOADFILE 0x00020000 // LoadFile
# DEBUG_EVENT 0x00080000 // Event messages
# DEBUG_GCD 0x00100000 // Global Coherency Database changes
# DEBUG_CACHE 0x00200000 // Memory range cachability changes
# DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
# // significantly impact boot performance
# DEBUG_ERROR 0x80000000 // Error
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x6E000000
gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x4809C000
# Console
gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3
# Timers
gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3
gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|77
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|13000000
# OMAP Interrupt Controller
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress|0x48200000
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
Omap35xxPkg/Library/OmapLib/OmapLib.inf
Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf
Omap35xxPkg/Flash/Flash.inf
Omap35xxPkg/MMCHSDxe/MMCHS.inf
Omap35xxPkg/SmbusDxe/Smbus.inf
Omap35xxPkg/Gpio/Gpio.inf
Omap35xxPkg/InterruptDxe/InterruptDxe.inf
Omap35xxPkg/TimerDxe/TimerDxe.inf
Omap35xxPkg/TPS65950Dxe/TPS65950.inf
Omap35xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.inf
Omap35xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf
Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf
Omap35xxPkg/MmcHostDxe/MmcHostDxe.inf
Omap35xxPkg/PciEmulation/PciEmulation.inf

107
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@@ -1,107 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/NonDiscoverableDeviceRegistrationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <TPS65950.h>
#include <Omap3530/Omap3530.h>
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
STATIC
EFI_STATUS
ConfigureUSBHost (
NON_DISCOVERABLE_DEVICE *Device
)
{
EFI_STATUS Status;
UINT8 Data = 0;
// Take USB host out of force-standby mode
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol
Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR (Status);
// Power the USB PHY
Data = VAUX_DEV_GRP_P1;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEV_GRP), 1, &Data);
ASSERT_EFI_ERROR(Status);
Data = VAUX_DEDICATED_18V;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);
ASSERT_EFI_ERROR (Status);
// Enable power to the USB hub
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR (Status);
// LEDAON controls the power to the USB host, PWM is disabled
Data &= ~LEDAPWM;
Data |= LEDAON;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
PciEmulationEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
UINT8 CapabilityLength;
UINT8 PhysicalPorts;
UINTN MemorySize;
CapabilityLength = MmioRead8 (USB_EHCI_HCCAPBASE);
PhysicalPorts = MmioRead32 (USB_EHCI_HCCAPBASE + 0x4) & 0x0000000F;
MemorySize = CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE +
4 * PhysicalPorts - 1;
return RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeEhci,
NonDiscoverableDeviceDmaTypeNonCoherent,
ConfigureUSBHost,
NULL,
1,
USB_EHCI_HCCAPBASE, MemorySize
);
}

41
Omap35xxPkg/PciEmulation/PciEmulation.inf
View File

@@ -1,41 +0,0 @@
/** @file
Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardPciEmulation
FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = PciEmulationEntryPoint
[Sources.common]
PciEmulation.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
BaseLib
DebugLib
IoLib
NonDiscoverableDeviceRegistrationLib
UefiBootServicesTableLib
UefiDriverEntryPoint
[Protocols]
gEmbeddedExternalDeviceProtocolGuid
[Depex]
gEfiMetronomeArchProtocolGuid AND
gEmbeddedExternalDeviceProtocolGuid

319
Omap35xxPkg/SmbusDxe/Smbus.c
View File

@@ -1,319 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Omap3530/Omap3530.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/SmbusHc.h>
#define MAX_RETRY 1000
//
// Internal Functions
//
STATIC
EFI_STATUS
WaitForBusBusy (
VOID
)
{
UINTN Retry = 0;
while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1);
if (Retry == MAX_RETRY) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
PollForStatus(
UINT16 StatusBit
)
{
UINTN Retry = 0;
while(Retry < MAX_RETRY) {
if (MmioRead16(I2C_STAT) & StatusBit) {
//Clear particular status bit from Status register.
MmioOr16(I2C_STAT, StatusBit);
break;
}
Retry++;
}
if (Retry == MAX_RETRY) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
ConfigureI2c (
VOID
)
{
//Program prescaler to obtain 12-MHz clock
MmioWrite16(I2C_PSC, 0x0000);
//Program SCLL and SCLH
//NOTE: Following values are the register dump after U-Boot code executed.
//We need to figure out how its calculated based on the I2C functional clock and I2C_PSC.
MmioWrite16(I2C_SCLL, 0x0035);
MmioWrite16(I2C_SCLH, 0x0035);
//Take the I2C controller out of reset.
MmioOr16(I2C_CON, I2C_EN);
//Initialize the I2C controller.
//Set I2C controller in Master mode.
MmioOr16(I2C_CON, MST);
//Enable interrupts for receive/transmit mode.
MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE));
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
I2CReadOneByte (
UINT8 *Data
)
{
EFI_STATUS Status;
//I2C bus status checking
Status = WaitForBusBusy();
if (EFI_ERROR(Status)) {
return Status;
}
//Poll till Receive ready bit is set.
Status = PollForStatus(RRDY);
if (EFI_ERROR(Status)) {
return Status;
}
*Data = MmioRead8(I2C_DATA);
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
I2CWriteOneByte (
UINT8 Data
)
{
EFI_STATUS Status;
//I2C bus status checking
Status = WaitForBusBusy();
if (EFI_ERROR(Status)) {
return Status;
}
//Data transfer
//Poll till Transmit ready bit is set
Status = PollForStatus(XRDY);
if (EFI_ERROR(Status)) {
return Status;
}
MmioWrite8(I2C_DATA, Data);
//Wait and check if the NACK is not set.
gBS->Stall(1000);
if (MmioRead16(I2C_STAT) & NACK) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
SmbusBlockRead (
OUT UINT8 *Buffer,
IN UINTN Length
)
{
UINTN Index = 0;
EFI_STATUS Status = EFI_SUCCESS;
//Transfer configuration for receiving data.
MmioWrite16(I2C_CNT, Length);
//Need stop bit before sending data.
MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT));
while (Index < Length) {
//Read a byte
Status = I2CReadOneByte(&Buffer[Index++]);
if (EFI_ERROR(Status)) {
return Status;
}
}
//Transfer completion
Status = PollForStatus(ARDY);
if (EFI_ERROR(Status)) {
return Status;
}
return Status;
}
STATIC
EFI_STATUS
SmbusBlockWrite (
IN UINT8 *Buffer,
IN UINTN Length
)
{
UINTN Index = 0;
EFI_STATUS Status = EFI_SUCCESS;
//Transfer configuration for transmitting data
MmioWrite16(I2C_CNT, Length);
MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP));
while (Index < Length) {
//Send a byte
Status = I2CWriteOneByte(Buffer[Index++]);
if (EFI_ERROR(Status)) {
return Status;
}
}
//Transfer completion
Status = PollForStatus(ARDY);
if (EFI_ERROR(Status)) {
return Status;
}
return Status;
}
//
// Public Functions.
//
EFI_STATUS
EFIAPI
SmbusExecute (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN CONST EFI_SMBUS_DEVICE_COMMAND Command,
IN CONST EFI_SMBUS_OPERATION Operation,
IN CONST BOOLEAN PecCheck,
IN OUT UINTN *Length,
IN OUT VOID *Buffer
)
{
UINT8 *ByteBuffer = Buffer;
EFI_STATUS Status = EFI_SUCCESS;
UINT8 SlaveAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress);
if (PecCheck) {
return EFI_UNSUPPORTED;
}
if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) {
return EFI_UNSUPPORTED;
}
//Set the Slave address.
MmioWrite16(I2C_SA, SlaveAddr);
if (Operation == EfiSmbusReadBlock) {
Status = SmbusBlockRead(ByteBuffer, *Length);
} else if (Operation == EfiSmbusWriteBlock) {
Status = SmbusBlockWrite(ByteBuffer, *Length);
}
return Status;
}
EFI_STATUS
EFIAPI
SmbusArpDevice (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN BOOLEAN ArpAll,
IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL,
IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
EFIAPI
SmbusGetArpMap (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN OUT UINTN *Length,
IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
EFIAPI
SmbusNotify (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN CONST UINTN Data,
IN CONST EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction
)
{
return EFI_UNSUPPORTED;
}
EFI_SMBUS_HC_PROTOCOL SmbusProtocol =
{
SmbusExecute,
SmbusArpDevice,
SmbusGetArpMap,
SmbusNotify
};
EFI_STATUS
InitializeSmbus (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
//Configure I2C controller.
Status = ConfigureI2c();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n"));
return Status;
}
// Install the SMBUS interface
Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL);
ASSERT_EFI_ERROR(Status);
return Status;
}

39
Omap35xxPkg/SmbusDxe/Smbus.inf
View File

@@ -1,39 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Smbus
FILE_GUID = d5125e0f-1226-444f-a218-0085996ed5da
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeSmbus
[Sources.common]
Smbus.c
[Packages]
MdePkg/MdePkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
[Guids]
[Protocols]
gEfiSmbusHcProtocolGuid
[Pcd]
[depex]
TRUE

110
Omap35xxPkg/TPS65950Dxe/TPS65950.c
View File

@@ -1,110 +0,0 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <TPS65950.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/SmbusHc.h>
EFI_SMBUS_HC_PROTOCOL *Smbus;
EFI_STATUS
Read (
IN EMBEDDED_EXTERNAL_DEVICE *This,
IN UINTN Register,
IN UINTN Length,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 DeviceRegister;
UINTN DeviceRegisterLength = 1;
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
//Write DeviceRegister.
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister);
if (EFI_ERROR(Status)) {
return Status;
}
//Read Data
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer);
return Status;
}
EFI_STATUS
Write (
IN EMBEDDED_EXTERNAL_DEVICE *This,
IN UINTN Register,
IN UINTN Length,
IN VOID *Buffer
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 DeviceRegister;
UINTN DeviceBufferLength = Length + 1;
UINT8 *DeviceBuffer;
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
//Prepare buffer for writing
DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength);
if (DeviceBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
//Set Device register followed by data to write.
DeviceBuffer[0] = DeviceRegister;
CopyMem(&DeviceBuffer[1], Buffer, Length);
//Write Data
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer);
if (EFI_ERROR(Status)) {
goto exit;
}
exit:
if (DeviceBuffer) {
FreePool(DeviceBuffer);
}
return Status;
}
EMBEDDED_EXTERNAL_DEVICE ExternalDevice = {
Read,
Write
};
EFI_STATUS
TPS65950Initialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus);
ASSERT_EFI_ERROR(Status);
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL);
return Status;
}

42
Omap35xxPkg/TPS65950Dxe/TPS65950.inf
View File

@@ -1,42 +0,0 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = TPS65950
FILE_GUID = 71fe861a-5450-48b6-bfb0-b93522616f99
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TPS65950Initialize
[Sources.common]
TPS65950.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
BaseMemoryLib
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
[Guids]
[Protocols]
gEfiSmbusHcProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Pcd]
[depex]
gEfiSmbusHcProtocolGuid

370
Omap35xxPkg/TimerDxe/Timer.c
View File

@@ -1,370 +0,0 @@
/** @file
Template for Timer Architecture Protocol driver of the ARM flavor
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Protocol/Timer.h>
#include <Protocol/HardwareInterrupt.h>
#include <Omap3530/Omap3530.h>
// The notification function to call on every timer interrupt.
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
// The current period of the timer interrupt
volatile UINT64 mTimerPeriod = 0;
// Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
// Cached registers
volatile UINT32 TISR;
volatile UINT32 TCLR;
volatile UINT32 TLDR;
volatile UINT32 TCRR;
volatile UINT32 TIER;
// Cached interrupt vector
volatile UINTN gVector;
/**
C Interrupt Handler calledin the interrupt context when Source interrupt is active.
@param Source Source of the interrupt. Hardware routing off a specific platform defines
what source means.
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
update the system context after the return from the interrupt if
modified. Don't change these values unless you know what you are doing
**/
VOID
EFIAPI
TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EFI_TPL OriginalTPL;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
// that raise to TPL_HIGH and then restore back to current level. Thus we need
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
//
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
if (mTimerNotifyFunction) {
mTimerNotifyFunction(mTimerPeriod);
}
// Clear all timer interrupts
MmioWrite32 (TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32 (TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
gBS->RestoreTPL (OriginalTPL);
}
/**
This function registers the handler NotifyFunction so it is called every time
the timer interrupt fires. It also passes the amount of time since the last
handler call to the NotifyFunction. If NotifyFunction is NULL, then the
handler is unregistered. If the handler is registered, then EFI_SUCCESS is
returned. If the CPU does not support registering a timer interrupt handler,
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
when a handler is already registered, then EFI_ALREADY_STARTED is returned.
If an attempt is made to unregister a handler when a handler is not registered,
then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
is returned.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param NotifyFunction The function to call when a timer interrupt fires. This
function executes at TPL_HIGH_LEVEL. The DXE Core will
register a handler for the timer interrupt, so it can know
how much time has passed. This information is used to
signal timer based events. NULL will unregister the handler.
@retval EFI_SUCCESS The timer handler was registered.
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
@retval EFI_DEVICE_ERROR The timer handler could not be registered.
**/
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN EFI_TIMER_NOTIFY NotifyFunction
)
{
if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
return EFI_ALREADY_STARTED;
}
mTimerNotifyFunction = NotifyFunction;
return EFI_SUCCESS;
}
/**
This function adjusts the period of timer interrupts to the value specified
by TimerPeriod. If the timer period is updated, then the selected timer
period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
If an error occurs while attempting to update the timer period, then the
timer hardware will be put back in its state prior to this call, and
EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
is disabled. This is not the same as disabling the CPU's interrupts.
Instead, it must either turn off the timer hardware, or it must adjust the
interrupt controller so that a CPU interrupt is not generated when the timer
interrupt fires.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is
returned. If the timer is programmable, then the timer period
will be rounded up to the nearest timer period that is supported
by the timer hardware. If TimerPeriod is set to 0, then the
timer interrupts will be disabled.
@retval EFI_SUCCESS The timer period was changed.
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
**/
EFI_STATUS
EFIAPI
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod
)
{
EFI_STATUS Status;
UINT64 TimerCount;
INT32 LoadValue;
if (TimerPeriod == 0) {
// Turn off GPTIMER3
MmioWrite32 (TCLR, TCLR_ST_OFF);
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
} else {
// Calculate required timer count
TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds));
// Set GPTIMER3 Load register
LoadValue = (INT32) -TimerCount;
MmioWrite32 (TLDR, LoadValue);
MmioWrite32 (TCRR, LoadValue);
// Enable Overflow interrupt
MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
}
//
// Save the new timer period
//
mTimerPeriod = TimerPeriod;
return Status;
}
/**
This function retrieves the period of timer interrupts in 100 ns units,
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
0 is returned, then the timer is currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
**/
EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
return EFI_INVALID_PARAMETER;
}
*TimerPeriod = mTimerPeriod;
return EFI_SUCCESS;
}
/**
This function generates a soft timer interrupt. If the platform does not support soft
timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
service, then a soft timer interrupt will be generated. If the timer interrupt is
enabled when this service is called, then the registered handler will be invoked. The
registered handler should not be able to distinguish a hardware-generated timer
interrupt from a software-generated timer interrupt.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@retval EFI_SUCCESS The soft timer interrupt was generated.
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
**/
EFI_STATUS
EFIAPI
TimerDriverGenerateSoftInterrupt (
IN EFI_TIMER_ARCH_PROTOCOL *This
)
{
return EFI_UNSUPPORTED;
}
/**
Interface stucture for the Timer Architectural Protocol.
@par Protocol Description:
This protocol provides the services to initialize a periodic timer
interrupt, and to register a handler that is called each time the timer
interrupt fires. It may also provide a service to adjust the rate of the
periodic timer interrupt. When a timer interrupt occurs, the handler is
passed the amount of time that has passed since the previous timer
interrupt.
@param RegisterHandler
Registers a handler that will be called each time the
timer interrupt fires. TimerPeriod defines the minimum
time between timer interrupts, so TimerPeriod will also
be the minimum time between calls to the registered
handler.
@param SetTimerPeriod
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period.
@param GetTimerPeriod
Retrieves the period of the timer interrupt in 100 nS units.
@param GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of
the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
a period of time.
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
TimerDriverGenerateSoftInterrupt
};
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
running program.
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINT32 TimerBaseAddress;
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Set up the timer registers
TimerBaseAddress = TimerBase (FixedPcdGet32(PcdOmap35xxArchTimer));
TISR = TimerBaseAddress + GPTIMER_TISR;
TCLR = TimerBaseAddress + GPTIMER_TCLR;
TLDR = TimerBaseAddress + GPTIMER_TLDR;
TCRR = TimerBaseAddress + GPTIMER_TCRR;
TIER = TimerBaseAddress + GPTIMER_TIER;
// Disable the timer
Status = TimerDriverSetTimerPeriod (&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install interrupt handler
gVector = InterruptVectorForTimer (FixedPcdGet32(PcdOmap35xxArchTimer));
Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// Turn on the functional clock for Timer
MmioOr32 (CM_FCLKEN_PER, CM_FCLKEN_PER_EN_GPT3_ENABLE);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
ASSERT_EFI_ERROR (Status);
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiTimerArchProtocolGuid, &gTimer,
NULL
);
ASSERT_EFI_ERROR(Status);
return Status;
}

51
Omap35xxPkg/TimerDxe/TimerDxe.inf
View File

@@ -1,51 +0,0 @@
#/** @file
#
# Component description file for Timer module
#
# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardTimerDxe
FILE_GUID = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TimerInitialize
[Sources.common]
Timer.c
[Packages]
Omap35xxPkg/Omap35xxPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
UefiRuntimeServicesTableLib
UefiLib
UefiBootServicesTableLib
BaseMemoryLib
DebugLib
UefiDriverEntryPoint
IoLib
OmapLib
[Guids]
[Protocols]
gEfiTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
[Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds
gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer
[Depex]
gHardwareInterruptProtocolGuid

279
OptionRomPkg/Application/BltLibSample/BltLibSample.c
View File

@@ -1,279 +0,0 @@
/** @file
Example program using BltLib
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BltLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiApplicationEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
UINT64
ReadTimestamp (
VOID
)
{
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
return AsmReadTsc ();
#else
#error ReadTimestamp not supported for this architecture!
#endif
}
UINT32
Rand32 (
VOID
)
{
UINTN Found;
INTN Bits;
UINT64 Tsc1;
UINT64 Tsc2;
UINT64 TscBits;
UINT32 R32;
R32 = 0;
Found = 0;
Tsc1 = ReadTimestamp ();
Tsc2 = ReadTimestamp ();
do {
Tsc2 = ReadTimestamp ();
TscBits = Tsc2 ^ Tsc1;
Bits = HighBitSet64 (TscBits);
if (Bits > 0) {
Bits = Bits - 1;
}
R32 = (UINT32)((R32 << Bits) |
RShiftU64 (LShiftU64 (TscBits, (UINTN) (64 - Bits)), (UINTN) (64 - Bits)));
Found = Found + Bits;
} while (Found < 32);
return R32;
}
VOID
TestFills (
VOID
)
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
UINTN Loop;
UINTN X;
UINTN Y;
UINTN W;
UINTN H;
UINTN Width;
UINTN Height;
BltLibGetSizes (&Width, &Height);
for (Loop = 0; Loop < 10000; Loop++) {
W = Width - (Rand32 () % Width);
H = Height - (Rand32 () % Height);
if (W != Width) {
X = Rand32 () % (Width - W);
} else {
X = 0;
}
if (H != Height) {
Y = Rand32 () % (Height - H);
} else {
Y = 0;
}
*(UINT32*) (&Color) = Rand32 () & 0xffffff;
BltLibVideoFill (&Color, X, Y, W, H);
}
}
VOID
TestColor1 (
VOID
)
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
UINTN X;
UINTN Y;
UINTN Width;
UINTN Height;
BltLibGetSizes (&Width, &Height);
*(UINT32*) (&Color) = 0;
for (Y = 0; Y < Height; Y++) {
for (X = 0; X < Width; X++) {
Color.Red = (UINT8) ((X * 0x100) / Width);
Color.Green = (UINT8) ((Y * 0x100) / Height);
Color.Blue = (UINT8) ((Y * 0x100) / Height);
BltLibVideoFill (&Color, X, Y, 1, 1);
}
}
}
UINT32
Uint32SqRt (
IN UINT32 Uint32
)
{
UINT32 Mask;
UINT32 SqRt;
UINT32 SqRtMask;
UINT32 Squared;
if (Uint32 == 0) {
return 0;
}
for (SqRt = 0, Mask = (UINT32) (1 << (HighBitSet32 (Uint32) / 2));
Mask != 0;
Mask = Mask >> 1
) {
SqRtMask = SqRt | Mask;
//DEBUG ((EFI_D_INFO, "Uint32=0x%x SqRtMask=0x%x\n", Uint32, SqRtMask));
Squared = (UINT32) (SqRtMask * SqRtMask);
if (Squared > Uint32) {
continue;
} else if (Squared < Uint32) {
SqRt = SqRtMask;
} else {
return SqRtMask;
}
}
return SqRt;
}
UINT32
Uint32Dist (
IN UINTN X,
IN UINTN Y
)
{
return Uint32SqRt ((UINT32) ((X * X) + (Y * Y)));
}
UINT8
GetTriColor (
IN UINTN ColorDist,
IN UINTN TriWidth
)
{
return (UINT8) (((TriWidth - ColorDist) * 0x100) / TriWidth);
//return (((TriWidth * TriWidth - ColorDist * ColorDist) * 0x100) / (TriWidth * TriWidth));
}
VOID
TestColor (
VOID
)
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
UINTN X, Y;
UINTN X1, X2, X3;
UINTN Y1, Y2;
UINTN LineWidth, TriWidth, ScreenWidth;
UINTN TriHeight, ScreenHeight;
UINT32 ColorDist;
BltLibGetSizes (&ScreenWidth, &ScreenHeight);
*(UINT32*) (&Color) = 0;
BltLibVideoFill (&Color, 0, 0, ScreenWidth, ScreenHeight);
TriWidth = (UINTN) DivU64x32 (
MultU64x32 (11547005, (UINT32) ScreenHeight),
10000000
);
TriHeight = (UINTN) DivU64x32 (
MultU64x32 (8660254, (UINT32) ScreenWidth),
10000000
);
if (TriWidth > ScreenWidth) {
DEBUG ((EFI_D_INFO, "TriWidth at %d was too big\n", TriWidth));
TriWidth = ScreenWidth;
} else if (TriHeight > ScreenHeight) {
DEBUG ((EFI_D_INFO, "TriHeight at %d was too big\n", TriHeight));
TriHeight = ScreenHeight;
}
DEBUG ((EFI_D_INFO, "Triangle Width: %d; Height: %d\n", TriWidth, TriHeight));
X1 = (ScreenWidth - TriWidth) / 2;
X3 = X1 + TriWidth - 1;
X2 = (X1 + X3) / 2;
Y2 = (ScreenHeight - TriHeight) / 2;
Y1 = Y2 + TriHeight - 1;
for (Y = Y2; Y <= Y1; Y++) {
LineWidth =
(UINTN) DivU64x32 (
MultU64x32 (11547005, (UINT32) (Y - Y2)),
20000000
);
for (X = X2 - LineWidth; X < (X2 + LineWidth); X++) {
ColorDist = Uint32Dist(X - X1, Y1 - Y);
Color.Red = GetTriColor (ColorDist, TriWidth);
ColorDist = Uint32Dist((X < X2) ? X2 - X : X - X2, Y - Y2);
Color.Green = GetTriColor (ColorDist, TriWidth);
ColorDist = Uint32Dist(X3 - X, Y1 - Y);
Color.Blue = GetTriColor (ColorDist, TriWidth);
BltLibVideoFill (&Color, X, Y, 1, 1);
}
}
}
/**
The user Entry Point for Application. The user code starts with this function
as the real entry point for the application.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
UefiMain (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop;
Status = gBS->HandleProtocol (
gST->ConsoleOutHandle,
&gEfiGraphicsOutputProtocolGuid,
(VOID **) &Gop
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = BltLibConfigure (
(VOID*)(UINTN) Gop->Mode->FrameBufferBase,
Gop->Mode->Info
);
if (EFI_ERROR (Status)) {
return Status;
}
TestFills ();
TestColor ();
return EFI_SUCCESS;
}

30
OptionRomPkg/Application/BltLibSample/BltLibSample.inf
View File

@@ -1,30 +0,0 @@
## @file
# Test the BltLib interface
#
# Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BltLibSample
FILE_GUID = f7763316-8c04-41d8-a87d-45b73c13c43c
MODULE_TYPE = UEFI_APPLICATION
VERSION_STRING = 1.0
ENTRY_POINT = UefiMain
[Sources]
BltLibSample.c
[Packages]
MdePkg/MdePkg.dec
OptionRomPkg/OptionRomPkg.dec
[LibraryClasses]
BltLib
UefiApplicationEntryPoint
UefiLib

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