ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM Support values to match PCIe Base Spec rev 3.0
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Phillips <chrisp@hp.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14892 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,6 +1,7 @@
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/** @file
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Header file for Pci shell Debug1 function.
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Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
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Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -157,7 +158,7 @@ typedef enum {
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//
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// Link Capabilities Register
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//
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#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \
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#define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \
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((PcieLinkCap) & 0x0f)
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#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
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(((PcieLinkCap) >> 4) & 0x3f)
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