IntelFsp2Pkg: Fsp T new ARCH UPD Support

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chiu Chasel <chasel.chiu@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>

Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Reviewed-by: Chiu Chasel <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Duggapu Chinni B
2024-04-05 09:30:48 +05:30
committed by mergify[bot]
parent 932db9df0c
commit 543add1d41
14 changed files with 212 additions and 28 deletions

View File

@@ -6,6 +6,7 @@
**/
#include <PiPei.h>
#include <Register/Intel/Msr.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
@@ -119,3 +120,40 @@ FspGetSystemMemorySize (
Hob.Raw = GET_NEXT_HOB (Hob);
}
}
/**
Calculate TemporaryRam Size using Base address.
@param[in] TemporaryRamBase the address of target memory
@param[out] TemporaryRamSize the size of target memory
**/
VOID
EFIAPI
ReadTemporaryRamSize (
IN UINT32 TemporaryRamBase,
OUT UINT32 *TemporaryRamSize
)
{
MSR_IA32_MTRRCAP_REGISTER Msr;
UINT32 MsrNum;
UINT32 MsrNumEnd;
if (TemporaryRamBase == 0) {
return;
}
*TemporaryRamSize = 0;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
MsrNumEnd = MSR_IA32_MTRR_PHYSBASE0 + (2 * (Msr.Bits.VCNT));
for (MsrNum = MSR_IA32_MTRR_PHYSBASE0; MsrNum < MsrNumEnd; MsrNum += 2) {
if ((AsmReadMsr64 (MsrNum+1) & BIT11) != 0 ) {
if (TemporaryRamBase == (AsmReadMsr64 (MsrNum) & 0xFFFFF000)) {
*TemporaryRamSize = (~(AsmReadMsr64 (MsrNum + 1) & 0xFFFFF000) + 1);
break;
}
}
}
return;
}