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MdePkg/BaseLib: RISC-V: Add few more helper functions

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Sunil V L
2022-09-06 10:48:12 +05:30
committed by mergify[bot]
parent 8aeb405466
commit 550f196e82
6 changed files with 179 additions and 4 deletions
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31
MdePkg/Library/BaseLib/RiscV64/CpuScratch.S Normal file
View File

@@ -0,0 +1,31 @@
//------------------------------------------------------------------------------
//
// CPU scratch register related functions for RISC-V
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
#include <Register/RiscV64/RiscVImpl.h>
.data
.align 3
.section .text
//
// Set Supervisor mode scratch.
// @param a0 : Value set to Supervisor mode scratch
//
ASM_FUNC (RiscVSetSupervisorScratch)
csrw CSR_SSCRATCH, a0
ret
//
// Get Supervisor mode scratch.
// @retval a0 : Value in Supervisor mode scratch
//
ASM_FUNC (RiscVGetSupervisorScratch)
csrr a0, CSR_SSCRATCH
ret