MdeModulePkg DxeIpl: Add stack NX support
This feature is added for UEFI spec that says "Stack may be marked as non-executable in identity mapped page tables". A PCD PcdSetNxForStack is added to turn on/off this feature, and it is FALSE by default. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18166 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -7,7 +7,7 @@
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -73,6 +73,28 @@ typedef union {
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 4KB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 PAT:1; //
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_4K_ENTRY;
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//
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// Page Table Entry 2MB
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//
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@@ -123,22 +145,49 @@ typedef union {
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#pragma pack()
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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/**
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Enable Execute Disable Bit.
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**/
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VOID
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EnableExecuteDisableBit (
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VOID
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);
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/**
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Split 2M page to 4K.
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@param[in] PhysicalAddress Start physical address the 2M page covered.
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@param[in, out] PageEntry2M Pointer to 2M page entry.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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**/
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VOID
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Split2MPageTo4K (
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IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
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IN OUT UINT64 *PageEntry2M,
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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);
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param NumberOfProcessorPhysicalAddressBits Number of processor address bits
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to use. Limits the number of page
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table entries to the physical
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address space.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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@return The address of 4 level page map.
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**/
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UINTN
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CreateIdentityMappingPageTables (
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VOID
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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);
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