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MdeModulePkg/SdMmcPciHcDxe: add Bayhub support

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Add support for Bayhub eMMC controller found on AMD
Stoneyridge Chromebooks.

Test: build/boot various google/kahlee-based devices

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Matt DeVillier
2020-01-06 16:15:51 -06:00
committed by Tim Crawford
parent e167ed1a3d
commit 587653cd8b
6 changed files with 708 additions and 15 deletions
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33
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
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@@ -305,6 +305,13 @@ SdMmcPciHcEnumerateDevice (
continue;
}
if (BhtHostPciSupport(Private->PciIo)) {
Status = SdMmcHcGetCapability (Private->PciIo, Slot, &Private->Capability[Slot]);
if (EFI_ERROR (Status)) {
continue;
}
}
Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
@@ -321,6 +328,7 @@ SdMmcPciHcEnumerateDevice (
// This card doesn't get initialized correctly.
//
if (Index == RoutineNum) {
DEBUG ((DEBUG_INFO, "Load driver failure\n"));
Private->Slot[Slot].Initialized = FALSE;
}
@@ -541,6 +549,8 @@ SdMmcPciHcDriverBindingStart (
UINT32 RoutineNum;
BOOLEAN MediaPresent;
BOOLEAN Support64BitDma;
UINT16 IntStatus;
UINT32 value;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -735,6 +745,13 @@ SdMmcPciHcDriverBindingStart (
continue;
}
if (BhtHostPciSupport(PciIo)) {
Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]);
if (EFI_ERROR (Status)) {
continue;
}
}
Private->Slot[Slot].MediaPresent = TRUE;
Private->Slot[Slot].Initialized = TRUE;
RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (CARD_TYPE_DETECT_ROUTINE);
@@ -751,9 +768,25 @@ SdMmcPciHcDriverBindingStart (
// This card doesn't get initialized correctly.
//
if (Index == RoutineNum) {
DEBUG ((DEBUG_INFO, "Load driver failure\n"));
Private->Slot[Slot].Initialized = FALSE;
}
}
if (BhtHostPciSupport(Private->PciIo)) {
SdMmcHcRwMmio (Private->PciIo,0,0x110,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x114,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x1a8,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x1ac,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x1B0,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x1CC,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,0x040,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_HOST_CTRL1,TRUE,sizeof (IntStatus),&IntStatus);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_CLOCK_CTRL,TRUE,sizeof (IntStatus),&IntStatus);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_TIMEOUT_CTRL,TRUE,sizeof (IntStatus),&IntStatus);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (value),&value);
SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_HOST_CTRL2,TRUE,sizeof (IntStatus),&IntStatus);
}
//
// Enable 64-bit DMA support in the PCI layer if this controller