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MdeModulePkg/SdMmcPciHcDxe: add Bayhub support

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Add support for Bayhub eMMC controller found on AMD
Stoneyridge Chromebooks.

Test: build/boot various google/kahlee-based devices

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Matt DeVillier
2020-01-06 16:15:51 -06:00
committed by Tim Crawford
parent e167ed1a3d
commit 587653cd8b
6 changed files with 708 additions and 15 deletions
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29
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
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@@ -607,4 +607,33 @@ SdMmcSetDriverStrength (
IN SD_DRIVER_STRENGTH_TYPE DriverStrength
);
BOOLEAN
BhtHostPciSupport(EFI_PCI_IO_PROTOCOL *PciIo);
UINT32
PciBhtRead32(EFI_PCI_IO_PROTOCOL *PciIo, UINT32 offset);
void
PciBhtWrite32(EFI_PCI_IO_PROTOCOL *PciIo, UINT32 offset, UINT32 value);
void
PciBhtOr32(EFI_PCI_IO_PROTOCOL *PciIo, UINT32 offset, UINT32 value);
void
PciBhtAnd32(EFI_PCI_IO_PROTOCOL *PciIo, UINT32 offset, UINT32 value);
extern void
DbgNull(IN CONST CHAR16 * fmt, ...);
#define PCI_DEV_ID_RJ 0x8320
#define PCI_DEV_ID_SDS0 0x8420
#define PCI_DEV_ID_SDS1 0x8421
#define PCI_DEV_ID_FJ2 0x8520
#define PCI_DEV_ID_SB0 0x8620
#define PCI_DEV_ID_SB1 0x8621
// O2/BHT add BAR1 for PCIR mapping registers
// These registers is defined by O2/BHT, but we may follow name definition rule.
#define BHT_PCIRMappingVal (0x200) /* PCI CFG Space Register Mapping Value Register */
#define BHT_PCIRMappingCtl (0x204) /* PCI CFG Space Register Mapping Control Register */
#define BHT_PCIRMappingEn (0x208) /* PCI CFG Space Register Mapping Enable Register */
#define BHT_GPIOCTL (0x210) /* GPIO control register*/
#endif