Remove tabs from all text files in the package.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11295 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@@ -12,24 +12,24 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__ashldi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__ashldi3)
|
||||
\s\s
|
||||
ASM_PFX(__ashldi3):
|
||||
cmp r2, #31
|
||||
bls L2
|
||||
cmp r2, #63
|
||||
subls r2, r2, #32
|
||||
movls r2, r0, asl r2
|
||||
movhi r2, #0
|
||||
mov r1, r2
|
||||
mov r0, #0
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #31
|
||||
\s\sbls\s\sL2
|
||||
\s\scmp\s\sr2, #63
|
||||
\s\ssubls\s\sr2, r2, #32
|
||||
\s\smovls\s\sr2, r0, asl r2
|
||||
\s\smovhi\s\sr2, #0
|
||||
\s\smov\s\sr1, r2
|
||||
\s\smov\s\sr0, #0
|
||||
\s\sbx\s\slr
|
||||
L2:
|
||||
cmp r2, #0
|
||||
rsbne r3, r2, #32
|
||||
movne r3, r0, lsr r3
|
||||
movne r0, r0, asl r2
|
||||
orrne r1, r3, r1, asl r2
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #0
|
||||
\s\srsbne\s\sr3, r2, #32
|
||||
\s\smovne\s\sr3, r0, lsr r3
|
||||
\s\smovne\s\sr0, r0, asl r2
|
||||
\s\sorrne\s\sr1, r3, r1, asl r2
|
||||
\s\sbx\s\slr
|
||||
|
||||
@@ -12,25 +12,25 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__ashrdi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__ashrdi3)
|
||||
|
||||
ASM_PFX(__ashrdi3):
|
||||
cmp r2, #31
|
||||
bls L2
|
||||
cmp r2, #63
|
||||
subls r2, r2, #32
|
||||
mov ip, r1, asr #31
|
||||
movls r2, r1, asr r2
|
||||
movhi r2, ip
|
||||
mov r0, r2
|
||||
mov r1, ip
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #31
|
||||
\s\sbls\s\sL2
|
||||
\s\scmp\s\sr2, #63
|
||||
\s\ssubls\s\sr2, r2, #32
|
||||
\s\smov\s\sip, r1, asr #31
|
||||
\s\smovls\s\sr2, r1, asr r2
|
||||
\s\smovhi\s\sr2, ip
|
||||
\s\smov\s\sr0, r2
|
||||
\s\smov\s\sr1, ip
|
||||
\s\sbx\s\slr
|
||||
L2:
|
||||
cmp r2, #0
|
||||
rsbne r3, r2, #32
|
||||
movne r3, r1, asl r3
|
||||
movne r1, r1, asr r2
|
||||
orrne r0, r3, r0, lsr r2
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #0
|
||||
\s\srsbne\s\sr3, r2, #32
|
||||
\s\smovne\s\sr3, r1, asl r3
|
||||
\s\smovne\s\sr1, r1, asr r2
|
||||
\s\sorrne\s\sr0, r3, r0, lsr r2
|
||||
\s\sbx\s\slr
|
||||
|
||||
@@ -12,46 +12,46 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__clzsi2)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__clzsi2)
|
||||
|
||||
ASM_PFX(__clzsi2):
|
||||
@ frame_needed = 1, uses_anonymous_args = 0
|
||||
stmfd sp!, {r7, lr}
|
||||
add r7, sp, #0
|
||||
movs r3, r0, lsr #16
|
||||
movne r3, #16
|
||||
moveq r3, #0
|
||||
movne r9, #0
|
||||
moveq r9, #16
|
||||
mov r3, r0, lsr r3
|
||||
tst r3, #65280
|
||||
movne r0, #8
|
||||
moveq r0, #0
|
||||
movne lr, #0
|
||||
moveq lr, #8
|
||||
mov r3, r3, lsr r0
|
||||
tst r3, #240
|
||||
movne r0, #4
|
||||
moveq r0, #0
|
||||
movne ip, #0
|
||||
moveq ip, #4
|
||||
mov r3, r3, lsr r0
|
||||
tst r3, #12
|
||||
movne r0, #2
|
||||
moveq r0, #0
|
||||
movne r1, #0
|
||||
moveq r1, #2
|
||||
mov r2, r3, lsr r0
|
||||
add r3, lr, r9
|
||||
add r0, r3, ip
|
||||
add r1, r0, r1
|
||||
mov r0, r2, lsr #1
|
||||
eor r0, r0, #1
|
||||
ands r0, r0, #1
|
||||
mvnne r0, #0
|
||||
rsb r3, r2, #2
|
||||
and r0, r0, r3
|
||||
add r0, r1, r0
|
||||
ldmfd sp!, {r7, pc}
|
||||
\s\s@ frame_needed = 1, uses_anonymous_args = 0
|
||||
\s\sstmfd\s\ssp!, {r7, lr}
|
||||
\s\sadd\s\sr7, sp, #0
|
||||
\s\smovs\s\sr3, r0, lsr #16
|
||||
\s\smovne\s\sr3, #16
|
||||
\s\smoveq\s\sr3, #0
|
||||
\s\smovne\s\sr9, #0
|
||||
\s\smoveq\s\sr9, #16
|
||||
\s\smov\s\sr3, r0, lsr r3
|
||||
\s\stst\s\sr3, #65280
|
||||
\s\smovne\s\sr0, #8
|
||||
\s\smoveq\s\sr0, #0
|
||||
\s\smovne\s\slr, #0
|
||||
\s\smoveq\s\slr, #8
|
||||
\s\smov\s\sr3, r3, lsr r0
|
||||
\s\stst\s\sr3, #240
|
||||
\s\smovne\s\sr0, #4
|
||||
\s\smoveq\s\sr0, #0
|
||||
\s\smovne\s\sip, #0
|
||||
\s\smoveq\s\sip, #4
|
||||
\s\smov\s\sr3, r3, lsr r0
|
||||
\s\stst\s\sr3, #12
|
||||
\s\smovne\s\sr0, #2
|
||||
\s\smoveq\s\sr0, #0
|
||||
\s\smovne\s\sr1, #0
|
||||
\s\smoveq\s\sr1, #2
|
||||
\s\smov\s\sr2, r3, lsr r0
|
||||
\s\sadd\s\sr3, lr, r9
|
||||
\s\sadd\s\sr0, r3, ip
|
||||
\s\sadd\s\sr1, r0, r1
|
||||
\s\smov\s\sr0, r2, lsr #1
|
||||
\s\seor\s\sr0, r0, #1
|
||||
\s\sands\s\sr0, r0, #1
|
||||
\s\smvnne\s\sr0, #0
|
||||
\s\srsb\s\sr3, r2, #2
|
||||
\s\sand\s\sr0, r0, r3
|
||||
\s\sadd\s\sr0, r1, r0
|
||||
\s\sldmfd\s\ssp!, {r7, pc}
|
||||
|
||||
@@ -12,38 +12,38 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__ctzsi2)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__ctzsi2)
|
||||
\s\s
|
||||
ASM_PFX(__ctzsi2):
|
||||
uxth r3, r0
|
||||
cmp r3, #0
|
||||
moveq ip, #16
|
||||
movne ip, #0
|
||||
@ lr needed for prologue
|
||||
mov r0, r0, lsr ip
|
||||
tst r0, #255
|
||||
movne r3, #0
|
||||
moveq r3, #8
|
||||
mov r0, r0, lsr r3
|
||||
tst r0, #15
|
||||
movne r1, #0
|
||||
moveq r1, #4
|
||||
add r3, r3, ip
|
||||
mov r0, r0, lsr r1
|
||||
tst r0, #3
|
||||
movne r2, #0
|
||||
moveq r2, #2
|
||||
add r3, r3, r1
|
||||
mov r0, r0, lsr r2
|
||||
and r0, r0, #3
|
||||
add r2, r3, r2
|
||||
eor r3, r0, #1
|
||||
mov r0, r0, lsr #1
|
||||
ands r3, r3, #1
|
||||
mvnne r3, #0
|
||||
rsb r0, r0, #2
|
||||
and r0, r3, r0
|
||||
add r0, r2, r0
|
||||
bx lr
|
||||
\s\suxth\s\sr3, r0
|
||||
\s\scmp\s\sr3, #0
|
||||
\s\smoveq\s\sip, #16
|
||||
\s\smovne\s\sip, #0
|
||||
\s\s@ lr needed for prologue
|
||||
\s\smov\s\sr0, r0, lsr ip
|
||||
\s\stst\s\sr0, #255
|
||||
\s\smovne\s\sr3, #0
|
||||
\s\smoveq\s\sr3, #8
|
||||
\s\smov\s\sr0, r0, lsr r3
|
||||
\s\stst\s\sr0, #15
|
||||
\s\smovne\s\sr1, #0
|
||||
\s\smoveq\s\sr1, #4
|
||||
\s\sadd\s\sr3, r3, ip
|
||||
\s\smov\s\sr0, r0, lsr r1
|
||||
\s\stst\s\sr0, #3
|
||||
\s\smovne\s\sr2, #0
|
||||
\s\smoveq\s\sr2, #2
|
||||
\s\sadd\s\sr3, r3, r1
|
||||
\s\smov\s\sr0, r0, lsr r2
|
||||
\s\sand\s\sr0, r0, #3
|
||||
\s\sadd\s\sr2, r3, r2
|
||||
\s\seor\s\sr3, r0, #1
|
||||
\s\smov\s\sr0, r0, lsr #1
|
||||
\s\sands\s\sr3, r3, #1
|
||||
\s\smvnne\s\sr3, #0
|
||||
\s\srsb\s\sr0, r0, #2
|
||||
\s\sand\s\sr0, r3, r0
|
||||
\s\sadd\s\sr0, r2, r0
|
||||
\s\sbx\s\slr
|
||||
|
||||
@@ -12,38 +12,38 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__divdi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__divdi3)
|
||||
\s\s
|
||||
ASM_PFX(__divdi3):
|
||||
@ args = 0, pretend = 0, frame = 0
|
||||
@ frame_needed = 1, uses_anonymous_args = 0
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
mov r4, r3, asr #31
|
||||
add r7, sp, #8
|
||||
stmfd sp!, {r10, r11}
|
||||
mov r10, r1, asr #31
|
||||
sub sp, sp, #8
|
||||
mov r11, r10
|
||||
mov r5, r4
|
||||
eor r0, r0, r10
|
||||
eor r1, r1, r10
|
||||
eor r2, r2, r4
|
||||
eor r3, r3, r4
|
||||
subs r2, r2, r4
|
||||
sbc r3, r3, r5
|
||||
mov ip, #0
|
||||
subs r0, r0, r10
|
||||
sbc r1, r1, r11
|
||||
str ip, [sp, #0]
|
||||
bl ASM_PFX(__udivmoddi4)
|
||||
eor r2, r10, r4
|
||||
eor r3, r10, r4
|
||||
eor r0, r0, r2
|
||||
eor r1, r1, r3
|
||||
subs r0, r0, r2
|
||||
sbc r1, r1, r3
|
||||
sub sp, r7, #16
|
||||
ldmfd sp!, {r10, r11}
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\s@ args = 0, pretend = 0, frame = 0
|
||||
\s\s@ frame_needed = 1, uses_anonymous_args = 0
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\smov\s\sr4, r3, asr #31
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\sstmfd\s\ssp!, {r10, r11}
|
||||
\s\smov\s\sr10, r1, asr #31
|
||||
\s\ssub\s\ssp, sp, #8
|
||||
\s\smov\s\sr11, r10
|
||||
\s\smov\s\sr5, r4
|
||||
\s\seor\s\sr0, r0, r10
|
||||
\s\seor\s\sr1, r1, r10
|
||||
\s\seor\s\sr2, r2, r4
|
||||
\s\seor\s\sr3, r3, r4
|
||||
\s\ssubs\s\sr2, r2, r4
|
||||
\s\ssbc\s\sr3, r3, r5
|
||||
\s\smov\s\sip, #0
|
||||
\s\ssubs\s\sr0, r0, r10
|
||||
\s\ssbc\s\sr1, r1, r11
|
||||
\s\sstr\s\sip, [sp, #0]
|
||||
\s\sbl\s\sASM_PFX(__udivmoddi4)
|
||||
\s\seor\s\sr2, r10, r4
|
||||
\s\seor\s\sr3, r10, r4
|
||||
\s\seor\s\sr0, r0, r2
|
||||
\s\seor\s\sr1, r1, r3
|
||||
\s\ssubs\s\sr0, r0, r2
|
||||
\s\ssbc\s\sr1, r1, r3
|
||||
\s\ssub\s\ssp, r7, #16
|
||||
\s\sldmfd\s\ssp!, {r10, r11}
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
@@ -12,21 +12,21 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__divsi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__divsi3)
|
||||
\s\s
|
||||
ASM_PFX(__divsi3):
|
||||
eor r3, r0, r0, asr #31
|
||||
eor r2, r1, r1, asr #31
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
mov r5, r0, asr #31
|
||||
add r7, sp, #8
|
||||
mov r4, r1, asr #31
|
||||
sub r0, r3, r0, asr #31
|
||||
sub r1, r2, r1, asr #31
|
||||
bl ASM_PFX(__udivsi3)
|
||||
eor r1, r5, r4
|
||||
eor r0, r0, r1
|
||||
rsb r0, r1, r0
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\seor\s\sr3, r0, r0, asr #31
|
||||
\s\seor\s\sr2, r1, r1, asr #31
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\smov\s\sr5, r0, asr #31
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\smov\s\sr4, r1, asr #31
|
||||
\s\ssub\s\sr0, r3, r0, asr #31
|
||||
\s\ssub\s\sr1, r2, r1, asr #31
|
||||
\s\sbl\s\sASM_PFX(__udivsi3)
|
||||
\s\seor\s\sr1, r5, r4
|
||||
\s\seor\s\sr0, r0, r1
|
||||
\s\srsb\s\sr0, r1, r0
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
@@ -13,9 +13,9 @@
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__aeabi_ldivmod)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__aeabi_ldivmod)
|
||||
|
||||
//
|
||||
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
|
||||
|
||||
@@ -12,24 +12,24 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__lshrdi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__lshrdi3)
|
||||
\s\s
|
||||
ASM_PFX(__lshrdi3):
|
||||
cmp r2, #31
|
||||
bls L2
|
||||
cmp r2, #63
|
||||
subls r2, r2, #32
|
||||
movls r2, r1, lsr r2
|
||||
movhi r2, #0
|
||||
mov r0, r2
|
||||
mov r1, #0
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #31
|
||||
\s\sbls\s\sL2
|
||||
\s\scmp\s\sr2, #63
|
||||
\s\ssubls\s\sr2, r2, #32
|
||||
\s\smovls\s\sr2, r1, lsr r2
|
||||
\s\smovhi\s\sr2, #0
|
||||
\s\smov\s\sr0, r2
|
||||
\s\smov\s\sr1, #0
|
||||
\s\sbx\s\slr
|
||||
L2:
|
||||
cmp r2, #0
|
||||
rsbne r3, r2, #32
|
||||
movne r3, r1, asl r3
|
||||
movne r1, r1, lsr r2
|
||||
orrne r0, r3, r0, lsr r2
|
||||
bx lr
|
||||
\s\scmp\s\sr2, #0
|
||||
\s\srsbne\s\sr3, r2, #32
|
||||
\s\smovne\s\sr3, r1, asl r3
|
||||
\s\smovne\s\sr1, r1, lsr r2
|
||||
\s\sorrne\s\sr0, r3, r0, lsr r2
|
||||
\s\sbx\s\slr
|
||||
|
||||
@@ -12,23 +12,23 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(memcpy)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(memcpy)
|
||||
|
||||
ASM_PFX(memcpy):
|
||||
stmfd sp!, {r7, lr}
|
||||
mov ip, #0
|
||||
add r7, sp, #0
|
||||
mov lr, r0
|
||||
b L4
|
||||
\s\sstmfd\s\ssp!, {r7, lr}
|
||||
\s\smov\s\sip, #0
|
||||
\s\sadd\s\sr7, sp, #0
|
||||
\s\smov\s\slr, r0
|
||||
\s\sb\s\sL4
|
||||
L5:
|
||||
ldrb r3, [r1], #1 @ zero_extendqisi2
|
||||
add ip, ip, #1
|
||||
and r3, r3, #255
|
||||
strb r3, [lr], #1
|
||||
\s\sldrb\s\sr3, [r1], #1\s\s@ zero_extendqisi2
|
||||
\s\sadd\s\sip, ip, #1
|
||||
\s\sand\s\sr3, r3, #255
|
||||
\s\sstrb\s\sr3, [lr], #1
|
||||
L4:
|
||||
cmp ip, r2
|
||||
bne L5
|
||||
ldmfd sp!, {r7, pc}
|
||||
\s\scmp\s\sip, r2
|
||||
\s\sbne\s\sL5
|
||||
\s\sldmfd\s\ssp!, {r7, pc}
|
||||
|
||||
|
||||
@@ -14,23 +14,25 @@
|
||||
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT (memset)
|
||||
|
||||
ASM_PFX(memset):
|
||||
@ args = 0, pretend = 0, frame = 0
|
||||
@ frame_needed = 1, uses_anonymous_args = 0
|
||||
stmfd sp!, {r7, lr}
|
||||
mov ip, #0
|
||||
add r7, sp, #0
|
||||
mov lr, r0
|
||||
b L9
|
||||
L10:
|
||||
and r3, r1, #255
|
||||
add ip, ip, #1
|
||||
strb r3, [lr], #1
|
||||
L9:
|
||||
cmp ip, r2
|
||||
bne L10
|
||||
ldmfd sp!, {r7, pc}
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT (memset)
|
||||
|
||||
|
||||
ASM_PFX(memset):
|
||||
|
||||
\s\s@ args = 0, pretend = 0, frame = 0
|
||||
\s\s@ frame_needed = 1, uses_anonymous_args = 0
|
||||
\s\sstmfd\s\ssp!, {r7, lr}
|
||||
\s\smov\s\sip, #0
|
||||
\s\sadd\s\sr7, sp, #0
|
||||
\s\smov\s\slr, r0
|
||||
\s\sb\s\sL9
|
||||
L10:
|
||||
\s\sand\s\sr3, r1, #255
|
||||
\s\sadd\s\sip, ip, #1
|
||||
\s\sstrb\s\sr3, [lr], #1
|
||||
L9:
|
||||
\s\scmp\s\sip, r2
|
||||
\s\sbne\s\sL10
|
||||
\s\sldmfd\s\ssp!, {r7, pc}
|
||||
|
||||
|
||||
@@ -12,35 +12,35 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__moddi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__moddi3)
|
||||
|
||||
ASM_PFX(__moddi3):
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
mov r4, r1, asr #31
|
||||
add r7, sp, #8
|
||||
stmfd sp!, {r10, r11}
|
||||
mov r10, r3, asr #31
|
||||
sub sp, sp, #16
|
||||
mov r5, r4
|
||||
mov r11, r10
|
||||
eor r0, r0, r4
|
||||
eor r1, r1, r4
|
||||
eor r2, r2, r10
|
||||
eor r3, r3, r10
|
||||
add ip, sp, #8
|
||||
subs r0, r0, r4
|
||||
sbc r1, r1, r5
|
||||
subs r2, r2, r10
|
||||
sbc r3, r3, r11
|
||||
str ip, [sp, #0]
|
||||
bl ASM_PFX(__udivmoddi4)
|
||||
ldrd r0, [sp, #8]
|
||||
eor r0, r0, r4
|
||||
eor r1, r1, r4
|
||||
subs r0, r0, r4
|
||||
sbc r1, r1, r5
|
||||
sub sp, r7, #16
|
||||
ldmfd sp!, {r10, r11}
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\smov\s\sr4, r1, asr #31
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\sstmfd\s\ssp!, {r10, r11}
|
||||
\s\smov\s\sr10, r3, asr #31
|
||||
\s\ssub\s\ssp, sp, #16
|
||||
\s\smov\s\sr5, r4
|
||||
\s\smov\s\sr11, r10
|
||||
\s\seor\s\sr0, r0, r4
|
||||
\s\seor\s\sr1, r1, r4
|
||||
\s\seor\s\sr2, r2, r10
|
||||
\s\seor\s\sr3, r3, r10
|
||||
\s\sadd\s\sip, sp, #8
|
||||
\s\ssubs\s\sr0, r0, r4
|
||||
\s\ssbc\s\sr1, r1, r5
|
||||
\s\ssubs\s\sr2, r2, r10
|
||||
\s\ssbc\s\sr3, r3, r11
|
||||
\s\sstr\s\sip, [sp, #0]
|
||||
\s\sbl\s\sASM_PFX(__udivmoddi4)
|
||||
\s\sldrd\s\sr0, [sp, #8]
|
||||
\s\seor\s\sr0, r0, r4
|
||||
\s\seor\s\sr1, r1, r4
|
||||
\s\ssubs\s\sr0, r0, r4
|
||||
\s\ssbc\s\sr1, r1, r5
|
||||
\s\ssub\s\ssp, r7, #16
|
||||
\s\sldmfd\s\ssp!, {r10, r11}
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
@@ -12,16 +12,16 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__modsi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__modsi3)
|
||||
|
||||
ASM_PFX(__modsi3):
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
add r7, sp, #8
|
||||
mov r5, r0
|
||||
mov r4, r1
|
||||
bl ___divsi3
|
||||
mul r0, r4, r0
|
||||
rsb r0, r0, r5
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\smov\s\sr5, r0
|
||||
\s\smov\s\sr4, r1
|
||||
\s\sbl\s\s___divsi3
|
||||
\s\smul\s\sr0, r4, r0
|
||||
\s\srsb\s\sr0, r0, r5
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
@@ -12,47 +12,47 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__muldi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__muldi3)
|
||||
|
||||
ASM_PFX(__muldi3):
|
||||
stmfd sp!, {r4, r5, r6, r7, lr}
|
||||
add r7, sp, #12
|
||||
stmfd sp!, {r8, r10, r11}
|
||||
ldr r11, L4
|
||||
mov r4, r0, lsr #16
|
||||
and r8, r0, r11
|
||||
and ip, r2, r11
|
||||
mul lr, ip, r8
|
||||
mul ip, r4, ip
|
||||
sub sp, sp, #8
|
||||
add r10, ip, lr, lsr #16
|
||||
and ip, r10, r11
|
||||
and lr, lr, r11
|
||||
mov r6, r2, lsr #16
|
||||
str r4, [sp, #4]
|
||||
add r4, lr, ip, asl #16
|
||||
mul ip, r8, r6
|
||||
mov r5, r10, lsr #16
|
||||
add r10, ip, r4, lsr #16
|
||||
and ip, r10, r11
|
||||
and lr, r4, r11
|
||||
add r4, lr, ip, asl #16
|
||||
mul r0, r3, r0
|
||||
add ip, r5, r10, lsr #16
|
||||
ldr r5, [sp, #4]
|
||||
mla r0, r2, r1, r0
|
||||
mla r5, r6, r5, ip
|
||||
mov r10, r4
|
||||
add r11, r0, r5
|
||||
mov r1, r11
|
||||
mov r0, r4
|
||||
sub sp, r7, #24
|
||||
ldmfd sp!, {r8, r10, r11}
|
||||
ldmfd sp!, {r4, r5, r6, r7, pc}
|
||||
.p2align 2
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr}
|
||||
\s\sadd\s\sr7, sp, #12
|
||||
\s\sstmfd\s\ssp!, {r8, r10, r11}
|
||||
\s\sldr\s\sr11, L4
|
||||
\s\smov\s\sr4, r0, lsr #16
|
||||
\s\sand\s\sr8, r0, r11
|
||||
\s\sand\s\sip, r2, r11
|
||||
\s\smul\s\slr, ip, r8
|
||||
\s\smul\s\sip, r4, ip
|
||||
\s\ssub\s\ssp, sp, #8
|
||||
\s\sadd\s\sr10, ip, lr, lsr #16
|
||||
\s\sand\s\sip, r10, r11
|
||||
\s\sand\s\slr, lr, r11
|
||||
\s\smov\s\sr6, r2, lsr #16
|
||||
\s\sstr\s\sr4, [sp, #4]
|
||||
\s\sadd\s\sr4, lr, ip, asl #16
|
||||
\s\smul\s\sip, r8, r6
|
||||
\s\smov\s\sr5, r10, lsr #16
|
||||
\s\sadd\s\sr10, ip, r4, lsr #16
|
||||
\s\sand\s\sip, r10, r11
|
||||
\s\sand\s\slr, r4, r11
|
||||
\s\sadd\s\sr4, lr, ip, asl #16
|
||||
\s\smul\s\sr0, r3, r0
|
||||
\s\sadd\s\sip, r5, r10, lsr #16
|
||||
\s\sldr\s\sr5, [sp, #4]
|
||||
\s\smla\s\sr0, r2, r1, r0
|
||||
\s\smla\s\sr5, r6, r5, ip
|
||||
\s\smov\s\sr10, r4
|
||||
\s\sadd\s\sr11, r0, r5
|
||||
\s\smov\s\sr1, r11
|
||||
\s\smov\s\sr0, r4
|
||||
\s\ssub\s\ssp, r7, #24
|
||||
\s\sldmfd\s\ssp!, {r8, r10, r11}
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc}
|
||||
\s\s.p2align 2
|
||||
L5:
|
||||
.align 2
|
||||
\s\s.align 2
|
||||
L4:
|
||||
.long 65535
|
||||
\s\s.long\s\s65535
|
||||
|
||||
@@ -13,8 +13,8 @@
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
EXPORT __ARM_ll_mullu
|
||||
EXPORT __aeabi_lmul
|
||||
EXPORT\s\s__ARM_ll_mullu
|
||||
EXPORT\s\s__aeabi_lmul
|
||||
|
||||
AREA Math, CODE, READONLY
|
||||
|
||||
|
||||
@@ -14,16 +14,16 @@
|
||||
|
||||
|
||||
|
||||
EXPORT __ARM_switch8
|
||||
EXPORT\s\s__ARM_switch8
|
||||
|
||||
AREA ArmSwitch, CODE, READONLY
|
||||
|
||||
AREA\s\sArmSwitch, CODE, READONLY
|
||||
\s\s
|
||||
__ARM_switch8
|
||||
LDRB r12,[lr,#-1]
|
||||
CMP r3,r12
|
||||
LDRBCC r3,[lr,r3]
|
||||
LDRBCS r3,[lr,r12]
|
||||
ADD r12,lr,r3,LSL #1
|
||||
BX r12
|
||||
\s\sLDRB\s\s r12,[lr,#-1]
|
||||
\s\sCMP\s\s\s\s r3,r12
|
||||
\s\sLDRBCC\s\sr3,[lr,r3]
|
||||
\s\sLDRBCS\s\sr3,[lr,r12]
|
||||
\s\sADD\s\s\s\s r12,lr,r3,LSL #1
|
||||
\s\sBX\s\s\s\s r12
|
||||
|
||||
END
|
||||
|
||||
@@ -12,27 +12,27 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__ucmpdi2)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__ucmpdi2)
|
||||
\s\s
|
||||
ASM_PFX(__ucmpdi2):
|
||||
stmfd sp!, {r4, r5, r8, lr}
|
||||
cmp r1, r3
|
||||
mov r8, r0
|
||||
mov r4, r2
|
||||
mov r5, r3
|
||||
bcc L2
|
||||
bhi L4
|
||||
cmp r0, r2
|
||||
bcc L2
|
||||
movls r0, #1
|
||||
bls L8
|
||||
b L4
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r8, lr}
|
||||
\s\scmp\s\sr1, r3
|
||||
\s\smov\s\sr8, r0
|
||||
\s\smov\s\sr4, r2
|
||||
\s\smov\s\sr5, r3
|
||||
\s\sbcc\s\sL2
|
||||
\s\sbhi\s\sL4
|
||||
\s\scmp\s\sr0, r2
|
||||
\s\sbcc\s\sL2
|
||||
\s\smovls\s\sr0, #1
|
||||
\s\sbls\s\sL8
|
||||
\s\sb\s\sL4
|
||||
L2:
|
||||
mov r0, #0
|
||||
b L8
|
||||
\s\smov\s\sr0, #0
|
||||
\s\sb\s\sL8
|
||||
L4:
|
||||
mov r0, #2
|
||||
\s\smov\s\sr0, #2
|
||||
L8:
|
||||
ldmfd sp!, {r4, r5, r8, pc}
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r8, pc}
|
||||
|
||||
@@ -12,16 +12,16 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__udivdi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__udivdi3)
|
||||
|
||||
ASM_PFX(__udivdi3):
|
||||
stmfd sp!, {r7, lr}
|
||||
add r7, sp, #0
|
||||
sub sp, sp, #8
|
||||
mov ip, #0
|
||||
str ip, [sp, #0]
|
||||
bl ASM_PFX(__udivmoddi4)
|
||||
sub sp, r7, #0
|
||||
ldmfd sp!, {r7, pc}
|
||||
\s\sstmfd\s\ssp!, {r7, lr}
|
||||
\s\sadd\s\sr7, sp, #0
|
||||
\s\ssub\s\ssp, sp, #8
|
||||
\s\smov\s\sip, #0
|
||||
\s\sstr\s\sip, [sp, #0]
|
||||
\s\sbl\s\sASM_PFX(__udivmoddi4)
|
||||
\s\ssub\s\ssp, r7, #0
|
||||
\s\sldmfd\s\ssp!, {r7, pc}
|
||||
|
||||
@@ -12,231 +12,231 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__udivmoddi4)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__udivmoddi4)
|
||||
\s\s
|
||||
ASM_PFX(__udivmoddi4):
|
||||
stmfd sp!, {r4, r5, r6, r7, lr}
|
||||
add r7, sp, #12
|
||||
stmfd sp!, {r10, r11}
|
||||
sub sp, sp, #20
|
||||
stmia sp, {r2-r3}
|
||||
ldr r6, [sp, #48]
|
||||
orrs r2, r2, r3
|
||||
mov r10, r0
|
||||
mov r11, r1
|
||||
beq L2
|
||||
subs ip, r1, #0
|
||||
bne L4
|
||||
cmp r3, #0
|
||||
bne L6
|
||||
cmp r6, #0
|
||||
beq L8
|
||||
mov r1, r2
|
||||
bl ASM_PFX(__umodsi3)
|
||||
mov r1, #0
|
||||
stmia r6, {r0-r1}
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr}
|
||||
\s\sadd\s\sr7, sp, #12
|
||||
\s\sstmfd\s\ssp!, {r10, r11}
|
||||
\s\ssub\s\ssp, sp, #20
|
||||
\s\sstmia\s\ssp, {r2-r3}
|
||||
\s\sldr\s\sr6, [sp, #48]
|
||||
\s\sorrs\s\sr2, r2, r3
|
||||
\s\smov\s\sr10, r0
|
||||
\s\smov\s\sr11, r1
|
||||
\s\sbeq\s\sL2
|
||||
\s\ssubs\s\sip, r1, #0
|
||||
\s\sbne\s\sL4
|
||||
\s\scmp\s\sr3, #0
|
||||
\s\sbne\s\sL6
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sbeq\s\sL8
|
||||
\s\smov\s\sr1, r2
|
||||
\s\sbl\s\sASM_PFX(__umodsi3)
|
||||
\s\smov\s\sr1, #0
|
||||
\s\sstmia\s\sr6, {r0-r1}
|
||||
L8:
|
||||
ldr r1, [sp, #0]
|
||||
mov r0, r10
|
||||
b L45
|
||||
\s\sldr\s\sr1, [sp, #0]
|
||||
\s\smov\s\sr0, r10
|
||||
\s\sb\s\sL45
|
||||
L6:
|
||||
cmp r6, #0
|
||||
movne r1, #0
|
||||
stmneia r6, {r0-r1}
|
||||
b L2
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\smovne\s\sr1, #0
|
||||
\s\sstmneia\s\sr6, {r0-r1}
|
||||
\s\sb\s\sL2
|
||||
L4:
|
||||
ldr r1, [sp, #0]
|
||||
cmp r1, #0
|
||||
bne L12
|
||||
ldr r2, [sp, #4]
|
||||
cmp r2, #0
|
||||
bne L14
|
||||
cmp r6, #0
|
||||
beq L16
|
||||
mov r1, r2
|
||||
mov r0, r11
|
||||
bl ASM_PFX(__umodsi3)
|
||||
mov r1, #0
|
||||
stmia r6, {r0-r1}
|
||||
\s\sldr\s\sr1, [sp, #0]
|
||||
\s\scmp\s\sr1, #0
|
||||
\s\sbne\s\sL12
|
||||
\s\sldr\s\sr2, [sp, #4]
|
||||
\s\scmp\s\sr2, #0
|
||||
\s\sbne\s\sL14
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sbeq\s\sL16
|
||||
\s\smov\s\sr1, r2
|
||||
\s\smov\s\sr0, r11
|
||||
\s\sbl\s\sASM_PFX(__umodsi3)
|
||||
\s\smov\s\sr1, #0
|
||||
\s\sstmia\s\sr6, {r0-r1}
|
||||
L16:
|
||||
ldr r1, [sp, #4]
|
||||
mov r0, r11
|
||||
\s\sldr\s\sr1, [sp, #4]
|
||||
\s\smov\s\sr0, r11
|
||||
L45:
|
||||
bl ASM_PFX(__udivsi3)
|
||||
\s\sbl\s\sASM_PFX(__udivsi3)
|
||||
L46:
|
||||
mov r10, r0
|
||||
mov r11, #0
|
||||
b L10
|
||||
\s\smov\s\sr10, r0
|
||||
\s\smov\s\sr11, #0
|
||||
\s\sb\s\sL10
|
||||
L14:
|
||||
subs r1, r0, #0
|
||||
bne L18
|
||||
cmp r6, #0
|
||||
beq L16
|
||||
ldr r1, [sp, #4]
|
||||
mov r0, r11
|
||||
bl ASM_PFX(__umodsi3)
|
||||
mov r4, r10
|
||||
mov r5, r0
|
||||
stmia r6, {r4-r5}
|
||||
b L16
|
||||
\s\ssubs\s\sr1, r0, #0
|
||||
\s\sbne\s\sL18
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sbeq\s\sL16
|
||||
\s\sldr\s\sr1, [sp, #4]
|
||||
\s\smov\s\sr0, r11
|
||||
\s\sbl\s\sASM_PFX(__umodsi3)
|
||||
\s\smov\s\sr4, r10
|
||||
\s\smov\s\sr5, r0
|
||||
\s\sstmia\s\sr6, {r4-r5}
|
||||
\s\sb\s\sL16
|
||||
L18:
|
||||
sub r3, r2, #1
|
||||
tst r2, r3
|
||||
bne L22
|
||||
cmp r6, #0
|
||||
movne r4, r0
|
||||
andne r5, ip, r3
|
||||
stmneia r6, {r4-r5}
|
||||
\s\ssub\s\sr3, r2, #1
|
||||
\s\stst\s\sr2, r3
|
||||
\s\sbne\s\sL22
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\smovne\s\sr4, r0
|
||||
\s\sandne\s\sr5, ip, r3
|
||||
\s\sstmneia\s\sr6, {r4-r5}
|
||||
L24:
|
||||
rsb r3, r2, #0
|
||||
and r3, r2, r3
|
||||
clz r3, r3
|
||||
rsb r3, r3, #31
|
||||
mov r0, ip, lsr r3
|
||||
b L46
|
||||
\s\srsb\s\sr3, r2, #0
|
||||
\s\sand\s\sr3, r2, r3
|
||||
\s\sclz\s\sr3, r3
|
||||
\s\srsb\s\sr3, r3, #31
|
||||
\s\smov\s\sr0, ip, lsr r3
|
||||
\s\sb\s\sL46
|
||||
L22:
|
||||
clz r2, r2
|
||||
clz r3, ip
|
||||
rsb r3, r3, r2
|
||||
cmp r3, #30
|
||||
bhi L48
|
||||
rsb r2, r3, #31
|
||||
add lr, r3, #1
|
||||
mov r3, r1, asl r2
|
||||
str r3, [sp, #12]
|
||||
mov r3, r1, lsr lr
|
||||
ldr r0, [sp, #0]
|
||||
mov r5, ip, lsr lr
|
||||
orr r4, r3, ip, asl r2
|
||||
str r0, [sp, #8]
|
||||
b L29
|
||||
\s\sclz\s\sr2, r2
|
||||
\s\sclz\s\sr3, ip
|
||||
\s\srsb\s\sr3, r3, r2
|
||||
\s\scmp\s\sr3, #30
|
||||
\s\sbhi\s\sL48
|
||||
\s\srsb\s\sr2, r3, #31
|
||||
\s\sadd\s\slr, r3, #1
|
||||
\s\smov\s\sr3, r1, asl r2
|
||||
\s\sstr\s\sr3, [sp, #12]
|
||||
\s\smov\s\sr3, r1, lsr lr
|
||||
\s\sldr\s\sr0, [sp, #0]
|
||||
\s\smov\s\sr5, ip, lsr lr
|
||||
\s\sorr\s\sr4, r3, ip, asl r2
|
||||
\s\sstr\s\sr0, [sp, #8]
|
||||
\s\sb\s\sL29
|
||||
L12:
|
||||
ldr r3, [sp, #4]
|
||||
cmp r3, #0
|
||||
bne L30
|
||||
sub r3, r1, #1
|
||||
tst r1, r3
|
||||
bne L32
|
||||
cmp r6, #0
|
||||
andne r3, r3, r0
|
||||
movne r2, r3
|
||||
movne r3, #0
|
||||
stmneia r6, {r2-r3}
|
||||
\s\sldr\s\sr3, [sp, #4]
|
||||
\s\scmp\s\sr3, #0
|
||||
\s\sbne\s\sL30
|
||||
\s\ssub\s\sr3, r1, #1
|
||||
\s\stst\s\sr1, r3
|
||||
\s\sbne\s\sL32
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sandne\s\sr3, r3, r0
|
||||
\s\smovne\s\sr2, r3
|
||||
\s\smovne\s\sr3, #0
|
||||
\s\sstmneia\s\sr6, {r2-r3}
|
||||
L34:
|
||||
cmp r1, #1
|
||||
beq L10
|
||||
rsb r3, r1, #0
|
||||
and r3, r1, r3
|
||||
clz r3, r3
|
||||
rsb r0, r3, #31
|
||||
mov r1, ip, lsr r0
|
||||
rsb r3, r0, #32
|
||||
mov r0, r10, lsr r0
|
||||
orr ip, r0, ip, asl r3
|
||||
str r1, [sp, #12]
|
||||
str ip, [sp, #8]
|
||||
ldrd r10, [sp, #8]
|
||||
b L10
|
||||
\s\scmp\s\sr1, #1
|
||||
\s\sbeq\s\sL10
|
||||
\s\srsb\s\sr3, r1, #0
|
||||
\s\sand\s\sr3, r1, r3
|
||||
\s\sclz\s\sr3, r3
|
||||
\s\srsb\s\sr0, r3, #31
|
||||
\s\smov\s\sr1, ip, lsr r0
|
||||
\s\srsb\s\sr3, r0, #32
|
||||
\s\smov\s\sr0, r10, lsr r0
|
||||
\s\sorr\s\sip, r0, ip, asl r3
|
||||
\s\sstr\s\sr1, [sp, #12]
|
||||
\s\sstr\s\sip, [sp, #8]
|
||||
\s\sldrd\s\sr10, [sp, #8]
|
||||
\s\sb\s\sL10
|
||||
L32:
|
||||
clz r2, r1
|
||||
clz r3, ip
|
||||
rsb r3, r3, r2
|
||||
rsb r4, r3, #31
|
||||
mov r2, r0, asl r4
|
||||
mvn r1, r3
|
||||
and r2, r2, r1, asr #31
|
||||
add lr, r3, #33
|
||||
str r2, [sp, #8]
|
||||
add r2, r3, #1
|
||||
mov r3, r3, asr #31
|
||||
and r0, r3, r0, asl r1
|
||||
mov r3, r10, lsr r2
|
||||
orr r3, r3, ip, asl r4
|
||||
and r3, r3, r1, asr #31
|
||||
orr r0, r0, r3
|
||||
mov r3, ip, lsr lr
|
||||
str r0, [sp, #12]
|
||||
mov r0, r10, lsr lr
|
||||
and r5, r3, r2, asr #31
|
||||
rsb r3, lr, #31
|
||||
mov r3, r3, asr #31
|
||||
orr r0, r0, ip, asl r1
|
||||
and r3, r3, ip, lsr r2
|
||||
and r0, r0, r2, asr #31
|
||||
orr r4, r3, r0
|
||||
b L29
|
||||
\s\sclz\s\sr2, r1
|
||||
\s\sclz\s\sr3, ip
|
||||
\s\srsb\s\sr3, r3, r2
|
||||
\s\srsb\s\sr4, r3, #31
|
||||
\s\smov\s\sr2, r0, asl r4
|
||||
\s\smvn\s\sr1, r3
|
||||
\s\sand\s\sr2, r2, r1, asr #31
|
||||
\s\sadd\s\slr, r3, #33
|
||||
\s\sstr\s\sr2, [sp, #8]
|
||||
\s\sadd\s\sr2, r3, #1
|
||||
\s\smov\s\sr3, r3, asr #31
|
||||
\s\sand\s\sr0, r3, r0, asl r1
|
||||
\s\smov\s\sr3, r10, lsr r2
|
||||
\s\sorr\s\sr3, r3, ip, asl r4
|
||||
\s\sand\s\sr3, r3, r1, asr #31
|
||||
\s\sorr\s\sr0, r0, r3
|
||||
\s\smov\s\sr3, ip, lsr lr
|
||||
\s\sstr\s\sr0, [sp, #12]
|
||||
\s\smov\s\sr0, r10, lsr lr
|
||||
\s\sand\s\sr5, r3, r2, asr #31
|
||||
\s\srsb\s\sr3, lr, #31
|
||||
\s\smov\s\sr3, r3, asr #31
|
||||
\s\sorr\s\sr0, r0, ip, asl r1
|
||||
\s\sand\s\sr3, r3, ip, lsr r2
|
||||
\s\sand\s\sr0, r0, r2, asr #31
|
||||
\s\sorr\s\sr4, r3, r0
|
||||
\s\sb\s\sL29
|
||||
L30:
|
||||
clz r2, r3
|
||||
clz r3, ip
|
||||
rsb r3, r3, r2
|
||||
cmp r3, #31
|
||||
bls L37
|
||||
\s\sclz\s\sr2, r3
|
||||
\s\sclz\s\sr3, ip
|
||||
\s\srsb\s\sr3, r3, r2
|
||||
\s\scmp\s\sr3, #31
|
||||
\s\sbls\s\sL37
|
||||
L48:
|
||||
cmp r6, #0
|
||||
stmneia r6, {r10-r11}
|
||||
b L2
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sstmneia\s\sr6, {r10-r11}
|
||||
\s\sb\s\sL2
|
||||
L37:
|
||||
rsb r1, r3, #31
|
||||
mov r0, r0, asl r1
|
||||
add lr, r3, #1
|
||||
mov r2, #0
|
||||
str r0, [sp, #12]
|
||||
mov r0, r10, lsr lr
|
||||
str r2, [sp, #8]
|
||||
sub r2, r3, #31
|
||||
and r0, r0, r2, asr #31
|
||||
mov r3, ip, lsr lr
|
||||
orr r4, r0, ip, asl r1
|
||||
and r5, r3, r2, asr #31
|
||||
\s\srsb\s\sr1, r3, #31
|
||||
\s\smov\s\sr0, r0, asl r1
|
||||
\s\sadd\s\slr, r3, #1
|
||||
\s\smov\s\sr2, #0
|
||||
\s\sstr\s\sr0, [sp, #12]
|
||||
\s\smov\s\sr0, r10, lsr lr
|
||||
\s\sstr\s\sr2, [sp, #8]
|
||||
\s\ssub\s\sr2, r3, #31
|
||||
\s\sand\s\sr0, r0, r2, asr #31
|
||||
\s\smov\s\sr3, ip, lsr lr
|
||||
\s\sorr\s\sr4, r0, ip, asl r1
|
||||
\s\sand\s\sr5, r3, r2, asr #31
|
||||
L29:
|
||||
mov ip, #0
|
||||
mov r10, ip
|
||||
b L40
|
||||
\s\smov\s\sip, #0
|
||||
\s\smov\s\sr10, ip
|
||||
\s\sb\s\sL40
|
||||
L41:
|
||||
ldr r1, [sp, #12]
|
||||
ldr r2, [sp, #8]
|
||||
mov r3, r4, lsr #31
|
||||
orr r5, r3, r5, asl #1
|
||||
mov r3, r1, lsr #31
|
||||
orr r4, r3, r4, asl #1
|
||||
mov r3, r2, lsr #31
|
||||
orr r0, r3, r1, asl #1
|
||||
orr r1, ip, r2, asl #1
|
||||
ldmia sp, {r2-r3}
|
||||
str r0, [sp, #12]
|
||||
subs r2, r2, r4
|
||||
sbc r3, r3, r5
|
||||
str r1, [sp, #8]
|
||||
subs r0, r2, #1
|
||||
sbc r1, r3, #0
|
||||
mov r2, r1, asr #31
|
||||
ldmia sp, {r0-r1}
|
||||
mov r3, r2
|
||||
and ip, r2, #1
|
||||
and r3, r3, r1
|
||||
and r2, r2, r0
|
||||
subs r4, r4, r2
|
||||
sbc r5, r5, r3
|
||||
add r10, r10, #1
|
||||
\s\sldr\s\sr1, [sp, #12]
|
||||
\s\sldr\s\sr2, [sp, #8]
|
||||
\s\smov\s\sr3, r4, lsr #31
|
||||
\s\sorr\s\sr5, r3, r5, asl #1
|
||||
\s\smov\s\sr3, r1, lsr #31
|
||||
\s\sorr\s\sr4, r3, r4, asl #1
|
||||
\s\smov\s\sr3, r2, lsr #31
|
||||
\s\sorr\s\sr0, r3, r1, asl #1
|
||||
\s\sorr\s\sr1, ip, r2, asl #1
|
||||
\s\sldmia\s\ssp, {r2-r3}
|
||||
\s\sstr\s\sr0, [sp, #12]
|
||||
\s\ssubs\s\sr2, r2, r4
|
||||
\s\ssbc\s\sr3, r3, r5
|
||||
\s\sstr\s\sr1, [sp, #8]
|
||||
\s\ssubs\s\sr0, r2, #1
|
||||
\s\ssbc\s\sr1, r3, #0
|
||||
\s\smov\s\sr2, r1, asr #31
|
||||
\s\sldmia\s\ssp, {r0-r1}
|
||||
\s\smov\s\sr3, r2
|
||||
\s\sand\s\sip, r2, #1
|
||||
\s\sand\s\sr3, r3, r1
|
||||
\s\sand\s\sr2, r2, r0
|
||||
\s\ssubs\s\sr4, r4, r2
|
||||
\s\ssbc\s\sr5, r5, r3
|
||||
\s\sadd\s\sr10, r10, #1
|
||||
L40:
|
||||
cmp r10, lr
|
||||
bne L41
|
||||
ldrd r0, [sp, #8]
|
||||
adds r0, r0, r0
|
||||
adc r1, r1, r1
|
||||
cmp r6, #0
|
||||
orr r10, r0, ip
|
||||
mov r11, r1
|
||||
stmneia r6, {r4-r5}
|
||||
b L10
|
||||
\s\scmp\s\sr10, lr
|
||||
\s\sbne\s\sL41
|
||||
\s\sldrd\s\sr0, [sp, #8]
|
||||
\s\sadds\s\sr0, r0, r0
|
||||
\s\sadc\s\sr1, r1, r1
|
||||
\s\scmp\s\sr6, #0
|
||||
\s\sorr\s\sr10, r0, ip
|
||||
\s\smov\s\sr11, r1
|
||||
\s\sstmneia\s\sr6, {r4-r5}
|
||||
\s\sb\s\sL10
|
||||
L2:
|
||||
mov r10, #0
|
||||
mov r11, #0
|
||||
\s\smov\s\sr10, #0
|
||||
\s\smov\s\sr11, #0
|
||||
L10:
|
||||
mov r0, r10
|
||||
mov r1, r11
|
||||
sub sp, r7, #20
|
||||
ldmfd sp!, {r10, r11}
|
||||
ldmfd sp!, {r4, r5, r6, r7, pc}
|
||||
\s\smov\s\sr0, r10
|
||||
\s\smov\s\sr1, r11
|
||||
\s\ssub\s\ssp, r7, #20
|
||||
\s\sldmfd\s\ssp!, {r10, r11}
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc}
|
||||
|
||||
@@ -12,46 +12,46 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__udivsi3)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__udivsi3)
|
||||
|
||||
ASM_PFX(__udivsi3):
|
||||
cmp r1, #0
|
||||
cmpne r0, #0
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
add r7, sp, #8
|
||||
beq L2
|
||||
clz r2, r1
|
||||
clz r3, r0
|
||||
rsb r3, r3, r2
|
||||
cmp r3, #31
|
||||
bhi L2
|
||||
ldmeqfd sp!, {r4, r5, r7, pc}
|
||||
add r5, r3, #1
|
||||
rsb r3, r3, #31
|
||||
mov lr, #0
|
||||
mov r2, r0, asl r3
|
||||
mov ip, r0, lsr r5
|
||||
mov r4, lr
|
||||
b L8
|
||||
\s\scmp\s\sr1, #0
|
||||
\s\scmpne\s\sr0, #0
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\sbeq\s\sL2
|
||||
\s\sclz\s\sr2, r1
|
||||
\s\sclz\s\sr3, r0
|
||||
\s\srsb\s\sr3, r3, r2
|
||||
\s\scmp\s\sr3, #31
|
||||
\s\sbhi\s\sL2
|
||||
\s\sldmeqfd\s\ssp!, {r4, r5, r7, pc}
|
||||
\s\sadd\s\sr5, r3, #1
|
||||
\s\srsb\s\sr3, r3, #31
|
||||
\s\smov\s\slr, #0
|
||||
\s\smov\s\sr2, r0, asl r3
|
||||
\s\smov\s\sip, r0, lsr r5
|
||||
\s\smov\s\sr4, lr
|
||||
\s\sb\s\sL8
|
||||
L9:
|
||||
mov r0, r2, lsr #31
|
||||
orr ip, r0, ip, asl #1
|
||||
orr r2, r3, lr
|
||||
rsb r3, ip, r1
|
||||
sub r3, r3, #1
|
||||
and r0, r1, r3, asr #31
|
||||
mov lr, r3, lsr #31
|
||||
rsb ip, r0, ip
|
||||
add r4, r4, #1
|
||||
\s\smov\s\sr0, r2, lsr #31
|
||||
\s\sorr\s\sip, r0, ip, asl #1
|
||||
\s\sorr\s\sr2, r3, lr
|
||||
\s\srsb\s\sr3, ip, r1
|
||||
\s\ssub\s\sr3, r3, #1
|
||||
\s\sand\s\sr0, r1, r3, asr #31
|
||||
\s\smov\s\slr, r3, lsr #31
|
||||
\s\srsb\s\sip, r0, ip
|
||||
\s\sadd\s\sr4, r4, #1
|
||||
L8:
|
||||
cmp r4, r5
|
||||
mov r3, r2, asl #1
|
||||
bne L9
|
||||
orr r0, r3, lr
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\scmp\s\sr4, r5
|
||||
\s\smov\s\sr3, r2, asl #1
|
||||
\s\sbne\s\sL9
|
||||
\s\sorr\s\sr0, r3, lr
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
L2:
|
||||
mov r0, #0
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\smov\s\sr0, #0
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
|
||||
@@ -14,9 +14,9 @@
|
||||
|
||||
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__aeabi_uldivmod)
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__aeabi_uldivmod)
|
||||
|
||||
//
|
||||
//UINT64
|
||||
|
||||
@@ -12,18 +12,18 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__umoddi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__umoddi3)
|
||||
\s\s
|
||||
ASM_PFX(__umoddi3):
|
||||
stmfd sp!, {r7, lr}
|
||||
add r7, sp, #0
|
||||
sub sp, sp, #16
|
||||
add ip, sp, #8
|
||||
str ip, [sp, #0]
|
||||
bl ASM_PFX(__udivmoddi4)
|
||||
ldrd r0, [sp, #8]
|
||||
sub sp, r7, #0
|
||||
ldmfd sp!, {r7, pc}
|
||||
\s\sstmfd\s\ssp!, {r7, lr}
|
||||
\s\sadd\s\sr7, sp, #0
|
||||
\s\ssub\s\ssp, sp, #16
|
||||
\s\sadd\s\sip, sp, #8
|
||||
\s\sstr\s\sip, [sp, #0]
|
||||
\s\sbl\s\sASM_PFX(__udivmoddi4)
|
||||
\s\sldrd\s\sr0, [sp, #8]
|
||||
\s\ssub\s\ssp, r7, #0
|
||||
\s\sldmfd\s\ssp!, {r7, pc}
|
||||
|
||||
|
||||
@@ -12,17 +12,17 @@
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
GCC_ASM_EXPORT(__umodsi3)
|
||||
|
||||
\s\s.text
|
||||
\s\s.align 2
|
||||
\s\sGCC_ASM_EXPORT(__umodsi3)
|
||||
\s\s
|
||||
ASM_PFX(__umodsi3):
|
||||
stmfd sp!, {r4, r5, r7, lr}
|
||||
add r7, sp, #8
|
||||
mov r5, r0
|
||||
mov r4, r1
|
||||
bl ASM_PFX(__udivsi3)
|
||||
mul r0, r4, r0
|
||||
rsb r0, r0, r5
|
||||
ldmfd sp!, {r4, r5, r7, pc}
|
||||
\s\sstmfd\s\ssp!, {r4, r5, r7, lr}
|
||||
\s\sadd\s\sr7, sp, #8
|
||||
\s\smov\s\sr5, r0
|
||||
\s\smov\s\sr4, r1
|
||||
\s\sbl \s\sASM_PFX(__udivsi3)
|
||||
\s\smul\s\sr0, r4, r0
|
||||
\s\srsb\s\sr0, r0, r5
|
||||
\s\sldmfd\s\ssp!, {r4, r5, r7, pc}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user