1. Add address check for "RegisterForRuntime" APIs of PciLib, PciCf8Lib, PciExpressLib, and PciSegmentLib.
2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class. 3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -5,7 +5,7 @@
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configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows
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access to PCI Segment #0.
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Copyright (c) 2006 - 2008, Intel Corporation<BR>
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Copyright (c) 2006 - 2009, Intel Corporation<BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
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If Address > 0x0FFFFFFF, then ASSERT().
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If the register specified by Address >= 0x100, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@@ -23,7 +23,7 @@
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access method. Modules will typically use the PCI Segment Library for its PCI configuration
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accesses when PCI Segments other than Segment #0 must be accessed.
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Copyright (c) 2006 - 2008, Intel Corporation
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Copyright (c) 2006 - 2009, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -67,7 +67,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Register a PCI device so PCI configuration registers may be accessed after
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SetVirtualAddressMap().
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If Address > 0x0FFFFFFF, then ASSERT().
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@@ -112,7 +112,7 @@ PciSegmentRead8 (
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Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
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Value is returned. This function must guarantee that all PCI read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param Value The value to write.
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@@ -969,7 +969,7 @@ PciSegmentBitFieldAndThenOr32 (
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and 16-bit PCI configuration read cycles may be used at the beginning and the
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end of the range.
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If StartAddress > 0x0FFFFFFF, then ASSERT().
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If any reserved bits in StartAddress are set, then ASSERT().
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If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
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If Size > 0 and Buffer is NULL, then ASSERT().
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@@ -1001,7 +1001,7 @@ PciSegmentReadBuffer (
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8-bit and 16-bit PCI configuration write cycles may be used at the beginning
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and the end of the range.
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If StartAddress > 0x0FFFFFFF, then ASSERT().
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If any reserved bits in StartAddress are set, then ASSERT().
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If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
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If Size > 0 and Buffer is NULL, then ASSERT().
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