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UefiCpuPkg/MtrrUnitTest: Update test to cover no-fixed-mtrr cases.

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Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>

Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Ray Ni
2022-09-29 16:19:26 +08:00
committed by mergify[bot]
parent 1ec374cb50
commit 5b76b4a9f9
2 changed files with 36 additions and 25 deletions
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37
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
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@@ -13,25 +13,30 @@ STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {
};
STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
{ 38, TRUE, TRUE, CacheUncacheable, 12 },
{ 38, TRUE, TRUE, CacheWriteBack, 12 },
{ 38, TRUE, TRUE, CacheWriteThrough, 12 },
{ 38, TRUE, TRUE, CacheWriteProtected, 12 },
{ 38, TRUE, TRUE, CacheWriteCombining, 12 },
{ 38, TRUE, TRUE, CacheUncacheable, 12 },
{ 38, TRUE, TRUE, CacheWriteBack, 12 },
{ 38, TRUE, TRUE, CacheWriteThrough, 12 },
{ 38, TRUE, TRUE, CacheWriteProtected, 12 },
{ 38, TRUE, TRUE, CacheWriteCombining, 12 },
{ 42, TRUE, TRUE, CacheUncacheable, 12 },
{ 42, TRUE, TRUE, CacheWriteBack, 12 },
{ 42, TRUE, TRUE, CacheWriteThrough, 12 },
{ 42, TRUE, TRUE, CacheWriteProtected, 12 },
{ 42, TRUE, TRUE, CacheWriteCombining, 12 },
{ 42, TRUE, TRUE, CacheUncacheable, 12 },
{ 42, TRUE, TRUE, CacheWriteBack, 12 },
{ 42, TRUE, TRUE, CacheWriteThrough, 12 },
{ 42, TRUE, TRUE, CacheWriteProtected, 12 },
{ 42, TRUE, TRUE, CacheWriteCombining, 12 },
{ 48, TRUE, TRUE, CacheUncacheable, 12 },
{ 48, TRUE, TRUE, CacheWriteBack, 12 },
{ 48, TRUE, TRUE, CacheWriteThrough, 12 },
{ 48, TRUE, TRUE, CacheWriteProtected, 12 },
{ 48, TRUE, TRUE, CacheWriteCombining, 12 },
{ 48, TRUE, TRUE, CacheUncacheable, 12 },
{ 48, TRUE, TRUE, CacheWriteBack, 12 },
{ 48, TRUE, TRUE, CacheWriteThrough, 12 },
{ 48, TRUE, TRUE, CacheWriteProtected, 12 },
{ 48, TRUE, TRUE, CacheWriteCombining, 12 },
{ 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME
{ 48, TRUE, FALSE, CacheUncacheable, 12 },
{ 48, TRUE, FALSE, CacheWriteBack, 12 },
{ 48, TRUE, FALSE, CacheWriteThrough, 12 },
{ 48, TRUE, FALSE, CacheWriteProtected, 12 },
{ 48, TRUE, FALSE, CacheWriteCombining, 12 },
{ 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME
};
UINT32 mFixedMtrrsIndex[] = {