sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Just like EhciDxe, do not reset host controller when debug capability is enabled in XhciDxe driver.

Browse Source 
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Elvin Li
2013-10-09 08:30:59 +00:00
committed by li-elvin
parent 980f3026e5
commit 5bcb62a409
4 changed files with 51 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
View File

@@ -164,6 +164,11 @@ XhcReset (
// Flow through, same behavior as Host Controller Reset
//
case EFI_USB_HC_RESET_HOST_CONTROLLER:
if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
Status = EFI_SUCCESS;
goto ON_EXIT;
}
//
// Host Controller must be Halt when Reset it
//
@@ -1755,7 +1760,8 @@ XhcCreateUsbHc (
ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
Xhc->ExtCapRegBase = ExtCapReg << 2;
Xhc->UsbLegSupOffset = XhcGetLegSupCapAddr (Xhc);
Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
@@ -1764,6 +1770,7 @@ XhcCreateUsbHc (
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
//
// Create AsyncRequest Polling Timer