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Just like EhciDxe, do not reset host controller when debug capability is enabled in XhciDxe driver.

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Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Elvin Li
2013-10-09 08:30:59 +00:00
committed by li-elvin
parent 980f3026e5
commit 5bcb62a409
4 changed files with 51 additions and 10 deletions
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20
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
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@ -571,16 +571,18 @@ XhcClearBiosOwnership (
}
/**
Calculate the XHCI legacy support capability register offset.
Calculate the offset of the XHCI capability.
@param Xhc The XHCI Instance.
@param CapId The XHCI Capability ID.
@return The offset of XHCI legacy support capability register.
**/
UINT32
XhcGetLegSupCapAddr (
IN USB_XHCI_INSTANCE *Xhc
XhcGetCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
)
{
UINT32 ExtCapOffset;
@ -594,7 +596,7 @@ XhcGetLegSupCapAddr (
// Check if the extended capability register's capability id is USB Legacy Support.
//
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
if ((Data & 0xFF) == 0x1) {
if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
//
@ -660,6 +662,8 @@ XhcResetHC (
{
EFI_STATUS Status;
Status = EFI_SUCCESS;
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));
//
// Host can only be reset when it is halt. If not so, halt it
@ -672,8 +676,12 @@ XhcResetHC (
}
}
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
}
return Status;
}