Just like EhciDxe, do not reset host controller when debug capability is enabled in XhciDxe driver.

Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Elvin Li
2013-10-09 08:30:59 +00:00
committed by li-elvin
parent 980f3026e5
commit 5bcb62a409
4 changed files with 51 additions and 10 deletions

View File

@@ -29,6 +29,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define USB_HUB_CLASS_CODE 0x09
#define USB_HUB_SUBCLASS_CODE 0x00
#define XHC_CAP_USB_LEGACY 0x01
#define XHC_CAP_USB_DEBUG 0x0A
//============================================//
// XHCI register offset //
//============================================//
@@ -67,6 +70,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
//
// Debug registers offset
//
#define XHC_DC_DCCTRL 0x20
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
@@ -447,6 +455,21 @@ XhcClearRuntimeRegBit (
IN UINT32 Bit
);
/**
Read XHCI extended capability register.
@param Xhc The XHCI Instance.
@param Offset The offset of the extended capability register.
@return The register content read
**/
UINT32
XhcReadExtCapReg (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT32 Offset
);
/**
Whether the XHCI host controller is halted.
@@ -524,16 +547,18 @@ XhcRunHC (
);
/**
Calculate the XHCI legacy support capability register offset.
Calculate the offset of the XHCI capability.
@param Xhc The XHCI Instance.
@param CapId The XHCI Capability ID.
@return The offset of XHCI legacy support capability register.
**/
UINT32
XhcGetLegSupCapAddr (
IN USB_XHCI_INSTANCE *Xhc
XhcGetCapabilityAddr (
IN USB_XHCI_INSTANCE *Xhc,
IN UINT8 CapId
);
#endif