Just like EhciDxe, do not reset host controller when debug capability is enabled in XhciDxe driver.
Signed-off-by: Elvin Li <elvin.li@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -29,6 +29,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#define USB_HUB_CLASS_CODE 0x09
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#define USB_HUB_SUBCLASS_CODE 0x00
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#define XHC_CAP_USB_LEGACY 0x01
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#define XHC_CAP_USB_DEBUG 0x0A
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//============================================//
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// XHCI register offset //
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//============================================//
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@@ -67,6 +70,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
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#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
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//
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// Debug registers offset
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//
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#define XHC_DC_DCCTRL 0x20
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#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
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#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
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@@ -447,6 +455,21 @@ XhcClearRuntimeRegBit (
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IN UINT32 Bit
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);
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/**
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Read XHCI extended capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the extended capability register.
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@return The register content read
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**/
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UINT32
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XhcReadExtCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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);
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/**
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Whether the XHCI host controller is halted.
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@@ -524,16 +547,18 @@ XhcRunHC (
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);
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/**
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Calculate the XHCI legacy support capability register offset.
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Calculate the offset of the XHCI capability.
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@param Xhc The XHCI Instance.
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@param CapId The XHCI Capability ID.
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@return The offset of XHCI legacy support capability register.
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**/
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UINT32
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XhcGetLegSupCapAddr (
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IN USB_XHCI_INSTANCE *Xhc
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XhcGetCapabilityAddr (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT8 CapId
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);
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#endif
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