Enable the 0-31 temporary IDT entries prior to activate the LongMode. If not enable the temporary IDT table, DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED may not work correctly till CPU DXE programs the IDT table.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3966 6f19259b-4bc3-4df7-8a09-765794883524

MdeModulePkg/Core/DxeIplPeim/Ia32/IdtVectorAsm.S

@@ -0,0 +1,88 @@
+/*
+;-------------------------------------------------------------------------------
+;
+; Copyright (c) 2007, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;
+; Module Name:
+;
+;   IdtVectorAsm.S
+; 
+; Abstract:
+; 
+;
+;--------------------------------------------------------------------   --------
+*/
+
+    .text
+    .code32
+
+
+    .align  8
+    .globl  ASM_PFX(AsmGetVectorTemplatInfo)
+    .globl 	ASM_PFX(AsmVectorFixup)
+/*
+;
+;-----------------------------------------------------------------------
+;  Template of IDT Vector Handlers. 
+;
+;-----------------------------------------------------------------------
+*/
+@VectorTemplateBase:
+        pushl %eax
+        .byte 0x6a    #  push #VectorNum
+@VectorNum:
+        .byte 0
+        movl  CommonInterruptEntry, %eax
+        jmp   *%eax
+@VectorTemplateEnd:
+
+
+ASM_PFX(AsmGetVectorTemplatInfo):
+        movl  4(%esp), %ecx
+        movl  $@VectorTemplateBase, (%ecx)
+        movl  $(@VectorTemplateEnd - @VectorTemplateBase), %eax
+        ret
+
+ASM_PFX(AsmVectorFixup):
+        movl  8(%esp), %eax
+        movl  4(%esp), %ecx
+        movb  %al, (@VectorNum - @VectorTemplateBase)(%ecx)
+        ret
+
+/*
+; The follow algorithm is used for the common interrupt routine.
+
+;
+; +---------------------+ <-- 16-byte aligned ensured by processor
+; +    Old SS           +
+; +---------------------+
+; +    Old RSP          +
+; +---------------------+
+; +    RFlags           +
+; +---------------------+
+; +    CS               +
+; +---------------------+
+; +    RIP              +
+; +---------------------+
+; +    Error Code       +
+; +---------------------+
+; +    Vector Number    +
+; +---------------------+
+*/
+
+CommonInterruptEntry: 
+        cli
+@@:
+        jmp   @@
+
+
+
+