ArmPlatformPkg/Sec: Allowed the Secondary Cores to set the Secure/Non Secure bits to their PPIs

The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524

ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf

@@ -52,3 +52,6 @@
   gArmTokenSpaceGuid.PcdTrustzoneSupport
 
   gArmTokenSpaceGuid.PcdL2x0ControllerBase
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore

ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c

@@ -32,9 +32,14 @@
 **/
 VOID
 ArmPlatformTrustzoneInit (
-  VOID
+  IN  UINTN                     MpId
   )
 {
+  // Nothing to do
+  if (!IS_PRIMARY_CORE(MpId)) {
+    return;
+  }
+
   //
   // Setup TZ Protection Controller
   //

ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c

@@ -31,7 +31,7 @@
 **/
 VOID
 ArmPlatformTrustzoneInit (
-  VOID
+  IN  UINTN                     MpId
   )
 {
   // No TZPC or TZASC on RTSM to initialize