ArmPlatformPkg/Sec: Allowed the Secondary Cores to set the Secure/Non Secure bits to their PPIs

The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524

ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullSec.c

@@ -25,9 +25,14 @@
 **/
 VOID
 ArmPlatformTrustzoneInit (
-  VOID
+  IN  UINTN                     MpId
   )
 {
+  // Secondary cores might have to set the Secure SGIs into the GICD_IGROUPR0
+  if (!IS_PRIMARY_CORE(MpId)) {
+    return;
+  }
+
   ASSERT(FALSE);
 }
 

ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullSec.inf

@@ -1,5 +1,5 @@
 #/* @file
-#  Copyright (c) 2011, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
 #  
 #  This program and the accompanying materials                          
 #  are licensed and made available under the terms and conditions of the BSD License         
@@ -37,3 +37,6 @@
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdFvBaseAddress
+
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+  gArmTokenSpaceGuid.PcdArmPrimaryCore