MdePkg/BaseSynchronizationLib: Add spin lock alignment for IA32/x64

From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock
or semaphore is suggested to be present within a cache line. If the processors
are based on Intel NetBurst microarchitecture, two cache lines are suggested.
This could minimize the bus traffic required to service locks.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c

@@ -0,0 +1,29 @@
+/** @file
+  Internal function to get spin lock alignment.
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/**
+  Internal function to retrieve the architecture specific spin lock alignment
+  requirements for optimal spin lock performance.
+
+  @return The architecture specific spin lock alignment.
+  
+**/
+UINTN
+InternalGetSpinLockProperties (
+  VOID
+  )
+{
+  return 32;
+}
+