SourceLevelDebugPkg/DebugAgent: Support IA32 processors without DE or FXSAVE/FXRESTOR

Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney
2015-04-27 19:53:36 +00:00
committed by mdkinney
parent ef530fe71f
commit 5f72e68c90
7 changed files with 71 additions and 14 deletions

View File

@ -1,7 +1,7 @@
/** @file
Supporting functions for X64 architecture.
Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -28,6 +28,7 @@ InitializeDebugIdt (
IA32_DESCRIPTOR IdtDescriptor;
UINTN Index;
UINT16 CodeSegment;
UINT32 RegEdx;
AsmReadIdtr (&IdtDescriptor);
@ -61,9 +62,13 @@ InitializeDebugIdt (
IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
//
// If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then
// Set DE flag in CR4 to enable IO breakpoint
//
AsmWriteCr4 (AsmReadCr4 () | BIT3);
AsmCpuid (1, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT2) != 0) {
AsmWriteCr4 (AsmReadCr4 () | BIT3);
}
}
/**