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UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Sahil Dureja <sahil.dureja@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
This commit is contained in:
Ashraf Ali S
2021-09-11 16:55:51 +05:30
committed by mergify[bot]
parent 89f7ed8b29
commit 60d8bb9f28
21 changed files with 186 additions and 48 deletions
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72
UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
View File

@@ -1,72 +0,0 @@
;------------------------------------------------------------------------------
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
;
; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
BITS 64
%define ALIGN_TOP_TO_4K_FOR_PAGING
%define PAGE_PRESENT 0x01
%define PAGE_READ_WRITE 0x02
%define PAGE_USER_SUPERVISOR 0x04
%define PAGE_WRITE_THROUGH 0x08
%define PAGE_CACHE_DISABLE 0x010
%define PAGE_ACCESSED 0x020
%define PAGE_DIRTY 0x040
%define PAGE_PAT 0x080
%define PAGE_GLOBAL 0x0100
%define PAGE_2M_MBO 0x080
%define PAGE_2M_PAT 0x01000
%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
PAGE_ACCESSED + \
PAGE_DIRTY + \
PAGE_READ_WRITE + \
PAGE_PRESENT)
%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
PAGE_READ_WRITE + \
PAGE_PRESENT)
%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
PAGE_PDP_ATTR)
%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
TopLevelPageDirectory:
;
; Top level Page Directory Pointers (1 * 512GB entry)
;
DQ PDP(0x1000)
;
; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
;
TIMES 0x1000-PGTBLS_OFFSET($) DB 0
DQ PDP(0x2000)
DQ PDP(0x3000)
DQ PDP(0x4000)
DQ PDP(0x5000)
;
; Page Table Entries (2048 * 2MB entries => 4GB)
;
TIMES 0x2000-PGTBLS_OFFSET($) DB 0
%assign i 0
%rep 0x800
DQ PTE_2MB(i)
%assign i i+1
%endrep
EndOfPageTables: