SecurityPkg:Tcg: Fix comment typos

"Triggle" is a typo. Replace it with "Trigger"

Cc: Long Qin <qin.long@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Long Qin <qin.long@intel.com>
This commit is contained in:
Zhang, Chao B
2018-07-16 15:12:15 +08:00
parent 4c6d0de7ba
commit 60ee3bd8db
2 changed files with 16 additions and 16 deletions

View File

@@ -259,12 +259,12 @@ DefinitionBlock (
If (LNot (And (MORD, 0x10))) If (LNot (And (MORD, 0x10)))
{ {
// //
// Triggle the SMI through ACPI _PTS method. // Trigger the SMI through ACPI _PTS method.
// //
Store (0x02, MCIP) Store (0x02, MCIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOB2)
} }
@@ -365,7 +365,7 @@ DefinitionBlock (
Store (0x02, PPIP) Store (0x02, PPIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
Return (FRET) Return (FRET)
@@ -396,7 +396,7 @@ DefinitionBlock (
Store (0x05, PPIP) Store (0x05, PPIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
@@ -428,7 +428,7 @@ DefinitionBlock (
} }
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
Return (FRET) Return (FRET)
@@ -442,7 +442,7 @@ DefinitionBlock (
Store (DerefOf (Index (Arg2, 0x00)), UCRQ) Store (DerefOf (Index (Arg2, 0x00)), UCRQ)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
@@ -476,12 +476,12 @@ DefinitionBlock (
Store (DerefOf (Index (Arg2, 0x00)), MORD) Store (DerefOf (Index (Arg2, 0x00)), MORD)
// //
// Triggle the SMI through ACPI _DSM method. // Trigger the SMI through ACPI _DSM method.
// //
Store (0x01, MCIP) Store (0x01, MCIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOB2)
Return (MRET) Return (MRET)

View File

@@ -95,12 +95,12 @@ DefinitionBlock (
If (LNot (And (MORD, 0x10))) If (LNot (And (MORD, 0x10)))
{ {
// //
// Triggle the SMI through ACPI _PTS method. // Trigger the SMI through ACPI _PTS method.
// //
Store (0x02, MCIP) Store (0x02, MCIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOB2)
} }
@@ -200,7 +200,7 @@ DefinitionBlock (
Store (0x02, PPIP) Store (0x02, PPIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
Return (FRET) Return (FRET)
@@ -231,7 +231,7 @@ DefinitionBlock (
Store (0x05, PPIP) Store (0x05, PPIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
@@ -259,7 +259,7 @@ DefinitionBlock (
Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (DerefOf (Index (Arg2, 0x00)), PPRQ)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
Return (FRET) Return (FRET)
@@ -273,7 +273,7 @@ DefinitionBlock (
Store (DerefOf (Index (Arg2, 0x00)), UCRQ) Store (DerefOf (Index (Arg2, 0x00)), UCRQ)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOB2)
@@ -307,12 +307,12 @@ DefinitionBlock (
Store (DerefOf (Index (Arg2, 0x00)), MORD) Store (DerefOf (Index (Arg2, 0x00)), MORD)
// //
// Triggle the SMI through ACPI _DSM method. // Trigger the SMI through ACPI _DSM method.
// //
Store (0x01, MCIP) Store (0x01, MCIP)
// //
// Triggle the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOB2)
Return (MRET) Return (MRET)