diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c index 60b8c96dda..0503dbce1e 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c @@ -283,7 +283,7 @@ SnpInitialize ( } // Initiate a PHY reset - Status = PhySoftReset (PHY_RESET_PMT | PHY_RESET_CHECK_LINK, Snp); + Status = PhySoftReset (PHY_RESET_PMT, Snp); if (EFI_ERROR (Status)) { Snp->Mode->State = EfiSimpleNetworkStopped; DEBUG ((EFI_D_WARN, "Warning: Link not ready after TimeOut. Check ethernet cable\n")); @@ -403,7 +403,7 @@ SnpReset ( } // Initiate a PHY reset - Status = PhySoftReset (PHY_RESET_PMT | PHY_RESET_CHECK_LINK, Snp); + Status = PhySoftReset (PHY_RESET_PMT, Snp); if (EFI_ERROR (Status)) { Snp->Mode->State = EfiSimpleNetworkStopped; return EFI_NOT_STARTED; diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c index 301c42ff18..9531b0ba2a 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.c @@ -491,7 +491,6 @@ PhySoftReset ( ) { UINT32 PmtCtrl = 0; - UINT32 LinkTo = 0; // PMT PHY reset takes precedence over BCR if (Flags & PHY_RESET_PMT) { @@ -513,20 +512,6 @@ PhySoftReset ( } } - // Check the link status - if (Flags & PHY_RESET_CHECK_LINK) { - LinkTo = 100000; // 2 second (could be 50% more) - while (EFI_ERROR (CheckLinkStatus (0, Snp)) && (LinkTo > 0)) { - gBS->Stall (LAN9118_STALL); - LinkTo--; - } - - // Timed out - if (LinkTo <= 0) { - return EFI_TIMEOUT; - } - } - // Clear and acknowledge all interrupts if (Flags & PHY_SOFT_RESET_CLEAR_INT) { MmioWrite32 (LAN9118_INT_EN, 0); diff --git a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h index 5bc4501c1a..424bdc5a85 100644 --- a/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h +++ b/EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeUtil.h @@ -115,8 +115,7 @@ SoftReset ( // Flags for PHY reset #define PHY_RESET_PMT BIT0 #define PHY_RESET_BCR BIT1 -#define PHY_RESET_CHECK_LINK BIT2 -#define PHY_SOFT_RESET_CLEAR_INT BIT3 +#define PHY_SOFT_RESET_CLEAR_INT BIT2 // Perform PHY software reset EFI_STATUS