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Armkg: Fix EDK2 coding style

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11734 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-06-03 09:18:48 +00:00
parent eeec69c5dc
commit 63adfb1129
6 changed files with 145 additions and 127 deletions
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143
ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
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@@ -22,66 +22,71 @@
#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)
// Initialize PL320 L2 Cache Controller
VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {
UINT32 Data;
UINT32 Revision;
UINT32 Aux;
UINT32 PfCtl;
UINT32 PwrCtl;
VOID
L2x0CacheInit (
IN UINTN L2x0Base,
IN BOOLEAN CacheEnabled
)
{
UINT32 Data;
UINT32 Revision;
UINT32 Aux;
UINT32 PfCtl;
UINT32 PwrCtl;
// Check if L2x0 is present and is an ARM implementation
Data = L2x0ReadReg(L2X0_CACHEID);
if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {
ASSERT(0);
return;
}
// Check if L2x0 is present and is an ARM implementation
Data = L2x0ReadReg(L2X0_CACHEID);
if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {
ASSERT(0);
return;
}
// Check if L2x0 is PL310
if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {
ASSERT(0);
return;
}
// Check if L2x0 is PL310
if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {
ASSERT(0);
return;
}
// RTL release
Revision = Data & 0x3F;
// RTL release
Revision = Data & 0x3F;
// Check if L2x0 is already enabled then we disable it
Data = L2x0ReadReg(L2X0_CTRL);
if (Data & L2X0_CTRL_ENABLED) {
L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);
}
// Check if L2x0 is already enabled then we disable it
Data = L2x0ReadReg(L2X0_CTRL);
if (Data & L2X0_CTRL_ENABLED) {
L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);
}
//
// Set up global configurations
//
//
// Set up global configurations
//
// Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO
Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;
// Use AWCACHE attributes for WA
Aux |= L2x0_AUXCTRL_AW_AWCACHE;
// Use default Size
Data = L2x0ReadReg(L2X0_AUXCTRL);
Aux |= Data & (0x7 << 17);
// Use default associativity
Aux |= Data & (0x1 << 16);
// Enabled I & D Prefetch
Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
if (Revision >= 5) {
// Prefetch Offset Register
PfCtl = L2x0ReadReg(L2X0_PFCTRL);
// - Prefetch increment set to 0
// - Prefetch dropping off
// - Double linefills off
L2x0WriteReg(L2X0_PFCTRL, PfCtl);
// Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO
Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;
// Use AWCACHE attributes for WA
Aux |= L2x0_AUXCTRL_AW_AWCACHE;
// Use default Size
Data = L2x0ReadReg(L2X0_AUXCTRL);
Aux |= Data & (0x7 << 17);
// Use default associativity
Aux |= Data & (0x1 << 16);
// Enabled I & D Prefetch
Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
// Power Control Register - L2X0_PWRCTRL
PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);
// - Standby when idle off
// - Dynamic clock gating off
// - Nc,NC-shared dropping off
L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
}
if (Revision >= 5) {
// Prefetch Offset Register
PfCtl = L2x0ReadReg(L2X0_PFCTRL);
// - Prefetch increment set to 0
// - Prefetch dropping off
// - Double linefills off
L2x0WriteReg(L2X0_PFCTRL, PfCtl);
// Power Control Register - L2X0_PWRCTRL
PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);
// - Standby when idle off
// - Dynamic clock gating off
// - Nc,NC-shared dropping off
L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
}
if (Revision >= 4) {
// Tag RAM Latency register
@@ -107,24 +112,24 @@ VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {
| L2_DATA_ACCESS_LATENCY;
}
// Write Auxiliary value
L2x0WriteReg(L2X0_AUXCTRL, Aux);
// Write Auxiliary value
L2x0WriteReg(L2X0_AUXCTRL, Aux);
//
// Invalidate all entries in cache
//
L2x0WriteReg(L2X0_INVWAY, 0xffff);
// Poll cache maintenance register until invalidate operation is complete
while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);
//
// Invalidate all entries in cache
//
L2x0WriteReg(L2X0_INVWAY, 0xffff);
// Poll cache maintenance register until invalidate operation is complete
while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);
// Write to the Lockdown D and Lockdown I Register 9 if required
// - Not required
// Write to the Lockdown D and Lockdown I Register 9 if required
// - Not required
// Clear any residual raw interrupts
L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);
// Clear any residual raw interrupts
L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);
// Enable the cache
if (CacheEnabled) {
L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);
}
// Enable the cache
if (CacheEnabled) {
L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);
}
}