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Armkg: Fix EDK2 coding style

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11734 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-06-03 09:18:48 +00:00
parent eeec69c5dc
commit 63adfb1129
6 changed files with 145 additions and 127 deletions
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2
ArmPkg/Drivers/CpuDxe/Exception.c
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@@ -187,7 +187,7 @@ InitializeExceptions (
Status = RegisterInterruptHandler (Index, NULL); Status = RegisterInterruptHandler (Index, NULL);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} else { } else {
// If the debugger has alread hooked put its vector back // If the debugger has already hooked put its vector back
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index]; VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
} }
} }

7
ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
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@@ -22,7 +22,12 @@
#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg) #define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)
// Initialize PL320 L2 Cache Controller // Initialize PL320 L2 Cache Controller
VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) { VOID
L2x0CacheInit (
IN UINTN L2x0Base,
IN BOOLEAN CacheEnabled
)
{
UINT32 Data; UINT32 Data;
UINT32 Revision; UINT32 Revision;
UINT32 Aux; UINT32 Aux;

4
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c
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@@ -50,8 +50,8 @@ ArmInvalidScu (
scu_base = ArmGetScuBaseAddress(); scu_base = ArmGetScuBaseAddress();
/* Invalidate all: write -1 to SCU Invalidate All register */ // Invalidate all: write -1 to SCU Invalidate All register
MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff); MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff);
/* Enable SCU */ // Enable SCU
MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1); MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1);
} }

12
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
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@@ -295,21 +295,21 @@ ASM_PFX(ArmWriteCPACR):
bx lr bx lr
ASM_PFX(ArmEnableVFP): ASM_PFX(ArmEnableVFP):
// Enable VFP registers # Enable VFP registers
mrc p15, 0, r0, c1, c0, 2 mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) orr r0, r0, #0x00f00000 @ Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2 mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC mov r0, #0x40000000 @ Set EN bit in FPEXC
mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly mcr p10,#0x7,r0,c8,c0,#0 @ msr FPEXC,r0 in ARM assembly
bx lr bx lr
ASM_PFX(ArmCallWFI): ASM_PFX(ArmCallWFI):
wfi wfi
bx lr bx lr
//Note: Return 0 in Uniprocessor implementation #Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar): ASM_PFX(ArmReadCbar):
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
bx lr bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb): ASM_PFX(ArmInvalidateInstructionAndDataTlb):

12
ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
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@@ -16,10 +16,18 @@
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
VOID ArmClearMPCoreMailbox() { VOID
ArmClearMPCoreMailbox (
VOID
)
{
MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue)); MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));
} }
UINTN ArmGetMPCoreMailbox() { UINTN
ArmGetMPCoreMailbox (
VOID
)
{
return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress)); return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));
} }

7
ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
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@@ -15,6 +15,11 @@
#include <Library/L2X0CacheLib.h> #include <Library/L2X0CacheLib.h>
// Initialize L2X0 Cache Controller // Initialize L2X0 Cache Controller
VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) { VOID
L2x0CacheInit (
IN UINTN L2x0Base,
IN BOOLEAN CacheEnabled
)
{
//No implementation //No implementation
} }