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UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

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https://bugzilla.tianocore.org/show_bug.cgi?id=555

Add JMP instruction in SmiEntry.S file that is missing.  This
updates SmiEntry.S to match the logic in SmiEntry.asm and
SmiEntry.nasm.

The default BUILDRULEORDER has .nasm higher priority than
.asm or .S, so this issue was not seen with MSFT or GCC
tool chain families.  The XCODE5 tool chain overrides the
BUILDRULEORDER with .S higher than .nasm, so this issue
was only seen when using XCODE5 tool chain when IA32 SMM
is enabled.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
(cherry picked from commit 0d0a19cb14)
This commit is contained in:
Michael Kinney
2017-05-11 15:35:21 -07:00
parent cb053bb8a3
commit 66a539b5d4
1 changed files with 2 additions and 1 deletions
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3
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
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@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# #
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
@@ -159,6 +159,7 @@ L13:
rdmsr rdmsr
orw $MSR_EFER_XD,%ax # enable NXE orw $MSR_EFER_XD,%ax # enable NXE
wrmsr wrmsr
jmp NxeDone
SkipNxe: SkipNxe:
subl $4, %esp subl $4, %esp
NxeDone: NxeDone: