CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver
Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will switch to use the standard PciBusDxe and PciHostBridgeDxe from MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib is added to collect pre-allocated PCI resources. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Maurice Ma
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CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
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CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
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/** @file
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Library instance of PciHostBridgeLib library class for coreboot.
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Copyright (C) 2016, Red Hat, Inc.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/PciLib.h>
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#include "PciHostBridge.h"
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STATIC
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CONST
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CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID(0x0A03), // HID
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0 // UID
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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};
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/**
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Initialize a PCI_ROOT_BRIDGE structure.
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@param[in] Supports Supported attributes.
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@param[in] Attributes Initial attributes.
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@param[in] AllocAttributes Allocation attributes.
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@param[in] RootBusNumber The bus number to store in RootBus.
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@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
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assigned to any subordinate bus found behind any
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PCI bridge hanging off this root bus.
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The caller is repsonsible for ensuring that
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RootBusNumber <= MaxSubBusNumber. If
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RootBusNumber equals MaxSubBusNumber, then the
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root bus has no room for subordinate buses.
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@param[in] Io IO aperture.
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@param[in] Mem MMIO aperture.
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@param[in] MemAbove4G MMIO aperture above 4G.
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@param[in] PMem Prefetchable MMIO aperture.
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@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
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@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
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caller) that should be filled in by this
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function.
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@retval EFI_SUCCESS Initialization successful. A device path
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consisting of an ACPI device path node, with
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UID = RootBusNumber, has been allocated and
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linked into RootBus.
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@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
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**/
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EFI_STATUS
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InitRootBridge (
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IN UINT64 Supports,
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IN UINT64 Attributes,
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IN UINT64 AllocAttributes,
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IN UINT8 RootBusNumber,
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IN UINT8 MaxSubBusNumber,
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IN PCI_ROOT_BRIDGE_APERTURE *Io,
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IN PCI_ROOT_BRIDGE_APERTURE *Mem,
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IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
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IN PCI_ROOT_BRIDGE_APERTURE *PMem,
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IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
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OUT PCI_ROOT_BRIDGE *RootBus
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)
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{
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CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
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//
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// Be safe if other fields are added to PCI_ROOT_BRIDGE later.
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//
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ZeroMem (RootBus, sizeof *RootBus);
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RootBus->Segment = 0;
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RootBus->Supports = Supports;
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RootBus->Attributes = Attributes;
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RootBus->DmaAbove4G = FALSE;
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RootBus->AllocationAttributes = AllocAttributes;
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RootBus->Bus.Base = RootBusNumber;
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RootBus->Bus.Limit = MaxSubBusNumber;
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CopyMem (&RootBus->Io, Io, sizeof (*Io));
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CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
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CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
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CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
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CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
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RootBus->NoExtendedConfigSpace = FALSE;
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DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
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&mRootBridgeDevicePathTemplate);
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if (DevicePath == NULL) {
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DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
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return EFI_OUT_OF_RESOURCES;
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}
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DevicePath->AcpiDevicePath.UID = RootBusNumber;
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RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
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DEBUG ((EFI_D_INFO,
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"%a: populated root bus %d, with room for %d subordinate bus(es)\n",
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__FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
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return EFI_SUCCESS;
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}
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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)
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{
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return ScanForRootBridges (Count);
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}
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/**
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Free the root bridge instances array returned from
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PciHostBridgeGetRootBridges().
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@param The root bridge instances array.
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@param The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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if (Bridges == NULL && Count == 0) {
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return;
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}
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ASSERT (Bridges != NULL && Count > 0);
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do {
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--Count;
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FreePool (Bridges[Count].DevicePath);
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} while (Count > 0);
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FreePool (Bridges);
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}
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource
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descriptors. The Configuration contains the resources
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for all the root bridges. The resource for each root
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bridge is terminated with END descriptor and an
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additional END is appended indicating the end of the
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entire resources. The resource descriptor field
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values follow the description in
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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//
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// coreboot UEFI Payload does not do PCI enumeration and should not call this
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// library interface.
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//
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ASSERT (FALSE);
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}
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