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QuarkPlatformPkg/PlatformInit: Fix recovery detection issues

Browse Source 
https://bugzilla.tianocore.org/show_bug.cgi?id=137
https://bugzilla.tianocore.org/show_bug.cgi?id=139

There are four supported methods to generate a boot mode of
BOOT_IN_RECOVERY_MODE on the Galileo platforms:

* Detect a corrupt FV
* Detect a forced recovery from the ForceRecovery UEFI application
  that sets a bit in a sticky R/W register
* The RESET button for the Arduino shield is held while the system
  is powered up
* The RESET button for the Arduino shield is held while the system
  is rebooted using the REBOOT button.

The logic in the PlatformInit module is cleaned up and updated to
support all three of the recovery detection methods.  The clean
ups include:

* Remove extra debug messages
* Remove user input from serial port

In addition, once one of the recovery methods is detected and a
boot mode of BOOT_IN_RECOVERY_MODE is set, the Galileo platforms
would get an error attempting to use the USB host controller to
detect and read a recovery image from a USB drive.  The issue is
the IMR protection registers are programmed to prevent DMA to
memory owned by the PEI Core. The IMR register programming is
updated to allow DMA to memory that is allocated by the recovery
modules using the PEI AllocatePages() service.

Cc: Kelly Steele <kelly.steele@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Kelly Steele <kelly.steele@intel.com>
This commit is contained in:
Michael Kinney
2016-10-03 11:13:42 -07:00
parent 9c3dea8dda
commit 69a0854b8f
6 changed files with 98 additions and 186 deletions
Download Patch File Download Diff File Expand all files Collapse all files

112
QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c
View File

@@ -554,7 +554,6 @@ InstallEfiMemory (
UINT64 PeiMemoryLength;
UINTN BufferSize;
UINTN PeiMemoryIndex;
UINTN RequiredMemSize;
EFI_RESOURCE_ATTRIBUTE_TYPE Attribute;
EFI_PHYSICAL_ADDRESS BadMemoryAddress;
EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable;
@@ -613,12 +612,6 @@ InstallEfiMemory (
);
ASSERT_EFI_ERROR (Status);
//
// Get required memory size for ACPI use. This helps to put ACPI memory on the topest
//
RequiredMemSize = 0;
RetriveRequiredMemorySize (PeiServices, &RequiredMemSize);
//
// Detect MOR request by the OS.
//
@@ -735,15 +728,14 @@ InstallEfiMemory (
//
Status = SetPlatformImrPolicy (
PeiMemoryBaseAddress,
PeiMemoryLength,
RequiredMemSize
PeiMemoryLength
);
ASSERT_EFI_ERROR (Status);
//
// Carve out the top memory reserved for ACPI
//
Status = PeiServicesInstallPeiMemory (PeiMemoryBaseAddress, (PeiMemoryLength - RequiredMemSize));
Status = PeiServicesInstallPeiMemory (PeiMemoryBaseAddress, PeiMemoryLength);
ASSERT_EFI_ERROR (Status);
BuildResourceDescriptorHob (
@@ -1073,69 +1065,6 @@ InstallS3Memory (
return EFI_SUCCESS;
}
/**
This function returns the size, in bytes, required for the DXE phase.
@param PeiServices PEI Services table.
@param Size Pointer to the size, in bytes, required for the DXE phase.
@return None
**/
VOID
RetriveRequiredMemorySize (
IN EFI_PEI_SERVICES **PeiServices,
OUT UINTN *Size
)
{
EFI_PEI_HOB_POINTERS Hob;
EFI_MEMORY_TYPE_INFORMATION *MemoryData;
UINT8 Index;
UINTN TempPageNum;
MemoryData = NULL;
TempPageNum = 0;
Index = 0;
PeiServicesGetHobList ((VOID **)&Hob.Raw);
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)
) {
MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));
break;
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
//
// Platform PEIM should supply such a information. Generic PEIM doesn't assume any default value
//
if (!MemoryData) {
return ;
}
while (MemoryData[Index].Type != EfiMaxMemoryType) {
//
// Accumulate default memory size requirements
//
TempPageNum += MemoryData[Index].NumberOfPages;
Index++;
}
if (TempPageNum == 0) {
return ;
}
//
// Add additional pages used by DXE memory manager
//
(*Size) = (TempPageNum + EDKII_DXE_MEM_SIZE_PAGES) * EFI_PAGE_SIZE;
return ;
}
/**
This function returns the memory ranges to be enabled, along with information
@@ -1481,7 +1410,6 @@ Done:
@param PeiMemoryBaseAddress Base address of memory allocated for PEI.
@param PeiMemoryLength Length in bytes of the PEI memory (includes ACPI memory).
@param RequiredMemSize Size in bytes of the ACPI/Runtime memory
@return EFI_SUCCESS The function completed successfully.
EFI_ACCESS_DENIED Access to IMRs failed.
@@ -1490,8 +1418,7 @@ Done:
EFI_STATUS
SetPlatformImrPolicy (
IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
IN UINT64 PeiMemoryLength,
IN UINTN RequiredMemSize
IN UINT64 PeiMemoryLength
)
{
UINT8 Index;
@@ -1514,17 +1441,6 @@ SetPlatformImrPolicy (
}
}
//
// Add IMR0 protection for the 'PeiMemory'
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR0,
(UINT32)(((RShiftU64(PeiMemoryBaseAddress, 8)) & IMRL_MASK) | IMR_EN),
(UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize + EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1) - 1), 8)) & IMRL_MASK),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM)
);
//
// Add IMR2 protection for shadowed RMU binary.
//
@@ -1547,28 +1463,6 @@ SetPlatformImrPolicy (
(UINT32)(CPU_SNOOP + CPU0_NON_SMM)
);
//
// Add IMR5 protection for the legacy S3 and AP Startup Vector region (below 1MB).
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR5,
(UINT32)(((RShiftU64(AP_STARTUP_VECTOR, 8)) & IMRL_MASK) | IMR_EN),
(UINT32)((RShiftU64((AP_STARTUP_VECTOR + EFI_PAGE_SIZE - 1), 8)) & IMRH_MASK),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM)
);
//
// Add IMR6 protection for the ACPI Reclaim/ACPI/Runtime Services.
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR6,
(UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize+EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1)), 8)) & IMRL_MASK) | IMR_EN),
(UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-EFI_PAGE_SIZE-1), 8)) & IMRH_MASK),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM),
(UINT32)(CPU_SNOOP + CPU0_NON_SMM)
);
//
// Enable IMR4 protection of eSRAM.
//