sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean up

Browse Source 
RegisterCpuInterruptHandler did not allow setting
exception handlers for anything beyond the timer IRQ.
Beyond that, it didn't meet the spec around handling
of inputs.

RiscVSupervisorModeTrapHandler now will invoke
set handlers for both exceptions and interrupts.
Two arrays of handlers are maintained - one for exceptions
and one for interrupts.

For unhandled traps, RiscVSupervisorModeTrapHandler dumps
state using the now implemented DumpCpuContext.

For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped
PC address (SEPC), just like on AArch64 (ELR). This is
necessary for X86EmulatorPkg to work as it allows a trap
handler to return execution to a different place. Add
SSTATUS/STVAL as well, at least for debugging purposes. There
is no value in hiding this.

Fix nested exception handling. Handler code should not
be saving SIE (the value is saved in SSTATUS.SPIE) or
directly restored (that's done by SRET). Save and
restore the entire SSTATUS and STVAL, too.

Cc: Daniel Schaefer <git@danielschaefer.me>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
This commit is contained in:
Andrei Warkentin
2023-02-17 18:42:29 -06:00
committed by mergify[bot]
parent 5ad2592ab3
commit 69da506c92
5 changed files with 260 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S
View File

@@ -20,14 +20,14 @@ SupervisorModeTrap:
sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
csrr t0, CSR_SSTATUS
and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)
sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
csrr t0, CSR_SEPC
sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
csrr t0, CSR_SIE
sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
csrr t0, CSR_STVAL
sd t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)
ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
sd zero, SMODE_TRAP_REGS_OFFSET(zero)(sp)
sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
@@ -59,6 +59,7 @@ SupervisorModeTrap:
sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
/* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
mv a0, sp
call RiscVSupervisorModeTrapHandler
/* Restore all general regisers except SP */
@@ -66,6 +67,7 @@ SupervisorModeTrap:
ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
@@ -93,13 +95,10 @@ SupervisorModeTrap:
ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
csrw CSR_SEPC, t0
ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
csrw CSR_SIE, t0
csrr t0, CSR_SSTATUS
ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
or t0, t0, t1
ld t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
csrw CSR_SSTATUS, t0
ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
ld t0, SMODE_TRAP_REGS_OFFSET(stval)(sp)
csrw CSR_STVAL, t0
ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
addi sp, sp, SMODE_TRAP_REGS_SIZE
sret