diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index 893bca495a..8cbd685ab5 100644
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -32,4 +32,9 @@
 //
 #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
 
+#define PIIX4_PMBA             0x40
+
+#define PIIX4_PMREGMISC        0x80
+#define PIIX4_PMREGMISC_PMIOSE   BIT0
+
 #endif
diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 91fb6e1d49..4f59a7c0e3 100644
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -25,10 +25,69 @@
 //
 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
 
+//
+// B/D/F/Type: 0/0/0/PCI
+//
+#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
+
+#define MCH_GGC               0x52
+#define MCH_GGC_IVD             BIT1
+
+#define MCH_SMRAM             0x9D
+#define MCH_SMRAM_D_LCK         BIT4
+#define MCH_SMRAM_G_SMRAME      BIT3
+
+#define MCH_ESMRAMC           0x9E
+#define MCH_ESMRAMC_H_SMRAME    BIT7
+#define MCH_ESMRAMC_E_SMERR     BIT6
+#define MCH_ESMRAMC_SM_CACHE    BIT5
+#define MCH_ESMRAMC_SM_L1       BIT4
+#define MCH_ESMRAMC_SM_L2       BIT3
+#define MCH_ESMRAMC_TSEG_8MB    BIT2
+#define MCH_ESMRAMC_TSEG_2MB    BIT1
+#define MCH_ESMRAMC_TSEG_1MB    0
+#define MCH_ESMRAMC_TSEG_MASK   (BIT2 | BIT1)
+#define MCH_ESMRAMC_T_EN        BIT0
+
+#define MCH_GBSM              0xA4
+#define MCH_GBSM_MB_SHIFT       20
+
+#define MCH_BGSM              0xA8
+#define MCH_BGSM_MB_SHIFT       20
+
+#define MCH_TSEGMB            0xAC
+#define MCH_TSEGMB_MB_SHIFT     20
+
+#define MCH_TOLUD             0xB0
+#define MCH_TOLUD_MB_SHIFT      4
+
 //
 // B/D/F/Type: 0/0x1f/0/PCI
 //
 #define POWER_MGMT_REGISTER_Q35(Offset) \
   PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
 
+#define ICH9_PMBASE               0x40
+#define ICH9_PMBASE_MASK            (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
+                                     BIT10 | BIT9  | BIT8  | BIT7)
+
+#define ICH9_ACPI_CNTL            0x44
+#define ICH9_ACPI_CNTL_ACPI_EN      BIT7
+
+#define ICH9_GEN_PMCON_1          0xA0
+#define ICH9_GEN_PMCON_1_SMI_LOCK   BIT4
+
+//
+// IO ports
+//
+#define ICH9_APM_CNT 0xB2
+#define ICH9_APM_STS 0xB3
+
+//
+// IO ports relative to PMBASE
+//
+#define ICH9_PMBASE_OFS_SMI_EN 0x30
+#define ICH9_SMI_EN_APMC_EN      BIT5
+#define ICH9_SMI_EN_GBL_SMI_EN   BIT0
+
 #endif