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ARM Packages: Force the SEC modules to be 2K aligned for AArch64

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The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.

A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
2014-07-15 09:24:25 +00:00
committed by oliviermartin
parent 9232ee5338
commit 6d0ca2577c
8 changed files with 53 additions and 36 deletions
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7
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
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@@ -1,7 +1,7 @@
/** @file
* Main file supporting the transition to PEI Core in Normal World for Versatile Express
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -86,8 +86,9 @@ CEntryPoint (
//
// Write VBAR - The Exception Vector table must be aligned to its requirement
//TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
//ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
// 'Align=4K' is defined into your FDF for this module.
ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.