Ported the EBC driver to use the MDE Base Math lib functions. Removed math functions from EBC driver. Need to check to see if MDE Math lib ASSERT behavior will cause any issues with EBC driver?
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1814 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
ajfish
@@ -339,14 +339,14 @@ Returns:
|
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UINT8 *Ptr;
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UINT8 *ThunkBase;
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UINT64 Addr;
|
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UINT64 Code[3]; // Code in a bundle
|
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UINT64 RegNum; // register number for MOVL
|
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UINT64 I; // bits of MOVL immediate data
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UINT64 Ic; // bits of MOVL immediate data
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UINT64 Imm5c; // bits of MOVL immediate data
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UINT64 Imm9d; // bits of MOVL immediate data
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UINT64 Imm7b; // bits of MOVL immediate data
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UINT64 Br; // branch register for loading and jumping
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UINT64 Code[3]; // Code in a bundle
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UINT64 RegNum; // register number for MOVL
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UINT64 I; // bits of MOVL immediate data
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UINT64 Ic; // bits of MOVL immediate data
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UINT64 Imm5c; // bits of MOVL immediate data
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UINT64 Imm9d; // bits of MOVL immediate data
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UINT64 Imm7b; // bits of MOVL immediate data
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UINT64 Br; // branch register for loading and jumping
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UINT64 *Data64Ptr;
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UINT32 ThunkSize;
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UINT32 Size;
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@@ -441,25 +441,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -474,14 +474,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64 (Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64 (Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -506,25 +506,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -539,14 +539,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64 (Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64 (Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -578,25 +578,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -610,14 +610,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64(Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64(Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -641,8 +641,8 @@ Returns:
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// register and user register (same user register as previous bundle).
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//
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Br = 6;
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Code[2] |= LeftShiftU64 (Br, 6);
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Code[2] |= LeftShiftU64 (RegNum, 13);
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Code[2] |= LShiftU64 (Br, 6);
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Code[2] |= LShiftU64 (RegNum, 13);
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WriteBundle ((VOID *) Ptr, 0x0d, Code[0], Code[1], Code[2]);
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//
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@@ -657,7 +657,7 @@ Returns:
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Code[0] = OPCODE_NOP;
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Code[1] = OPCODE_NOP;
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Code[2] = OPCODE_BR_COND_SPTK_FEW;
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Code[2] |= LeftShiftU64 (Br, 13);
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Code[2] |= LShiftU64 (Br, 13);
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WriteBundle ((VOID *) Ptr, 0x1d, Code[0], Code[1], Code[2]);
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//
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@@ -728,8 +728,8 @@ Returns:
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return EFI_INVALID_PARAMETER;
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}
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Low64 = LeftShiftU64 (Slot1, 46) | LeftShiftU64 (Slot0, 5) | Template;
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High64 = RightShiftU64 (Slot1, 18) | LeftShiftU64 (Slot2, 23);
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Low64 = LShiftU64 (Slot1, 46) | LShiftU64 (Slot0, 5) | Template;
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High64 = RShiftU64 (Slot1, 18) | LShiftU64 (Slot2, 23);
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//
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// Now write it all out
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@@ -737,13 +737,13 @@ Returns:
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BPtr = (UINT8 *) MemPtr;
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for (Index = 0; Index < 8; Index++) {
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*BPtr = (UINT8) Low64;
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Low64 = RightShiftU64 (Low64, 8);
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Low64 = RShiftU64 (Low64, 8);
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BPtr++;
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}
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for (Index = 0; Index < 8; Index++) {
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*BPtr = (UINT8) High64;
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High64 = RightShiftU64 (High64, 8);
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High64 = RShiftU64 (High64, 8);
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BPtr++;
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}
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@@ -814,21 +814,21 @@ Returns:
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goto Action;
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}
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CodeOne18 = RightShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;
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CodeOne18 = RShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;
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CodeOne23 = (*((UINT64 *)CalleeAddr + 3)) & 0x7FFFFF;
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CodeTwoI = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;
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CodeTwoIc = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;
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CodeTwo7b = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;
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CodeTwo5c = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;
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CodeTwo9d = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;
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CodeTwoI = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;
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CodeTwoIc = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;
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CodeTwo7b = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;
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CodeTwo5c = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;
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CodeTwo9d = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;
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TargetEbcAddr = CodeTwo7b
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| LeftShiftU64 (CodeTwo9d, 7)
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| LeftShiftU64 (CodeTwo5c, 16)
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| LeftShiftU64 (CodeTwoIc, 21)
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| LeftShiftU64 (CodeOne18, 22)
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| LeftShiftU64 (CodeOne23, 40)
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| LeftShiftU64 (CodeTwoI, 63)
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| LShiftU64 (CodeTwo9d, 7)
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| LShiftU64 (CodeTwo5c, 16)
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| LShiftU64 (CodeTwoIc, 21)
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| LShiftU64 (CodeOne18, 22)
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| LShiftU64 (CodeOne23, 40)
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| LShiftU64 (CodeTwoI, 63)
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;
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Action:
|
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@@ -1,375 +0,0 @@
|
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/*++
|
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|
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Copyright (c) 2006, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
Ipfmath.c
|
||||
|
||||
Abstract:
|
||||
|
||||
Math routines for IPF.
|
||||
|
||||
--*/
|
||||
|
||||
UINT64
|
||||
LeftShiftU64 (
|
||||
IN UINT64 Operand,
|
||||
IN UINT64 Count
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Left-shift a 64 bit value.
|
||||
|
||||
Arguments:
|
||||
|
||||
Operand - 64-bit value to shift
|
||||
Count - shift count
|
||||
|
||||
Returns:
|
||||
|
||||
Operand << Count
|
||||
|
||||
--*/
|
||||
{
|
||||
if (Count > 63) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return Operand << Count;
|
||||
}
|
||||
|
||||
UINT64
|
||||
RightShiftU64 (
|
||||
IN UINT64 Operand,
|
||||
IN UINT64 Count
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Right-shift a 64 bit value.
|
||||
|
||||
Arguments:
|
||||
|
||||
Operand - 64-bit value to shift
|
||||
Count - shift count
|
||||
|
||||
Returns:
|
||||
|
||||
Operand >> Count
|
||||
|
||||
--*/
|
||||
{
|
||||
if (Count > 63) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return Operand >> Count;
|
||||
}
|
||||
|
||||
INT64
|
||||
ARightShift64 (
|
||||
IN INT64 Operand,
|
||||
IN UINT64 Count
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Right-shift a 64 bit signed value.
|
||||
|
||||
Arguments:
|
||||
|
||||
Operand - 64-bit value to shift
|
||||
Count - shift count
|
||||
|
||||
Returns:
|
||||
|
||||
Operand >> Count
|
||||
|
||||
--*/
|
||||
{
|
||||
if (Count > 63) {
|
||||
|
||||
if (Operand & (0x01 << 63)) {
|
||||
return (INT64)~0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return Operand >> Count;
|
||||
}
|
||||
|
||||
#if 0
|
||||
//
|
||||
// The compiler generates true assembly for these, so we don't need them.
|
||||
//
|
||||
INT32
|
||||
ARightShift32 (
|
||||
IN INT32 Operand,
|
||||
IN UINTN Count
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Right shift a 32-bit value
|
||||
|
||||
Arguments:
|
||||
|
||||
Operand - value to shift
|
||||
Count - shift count
|
||||
|
||||
Returns:
|
||||
|
||||
Operand >> Count
|
||||
|
||||
--*/
|
||||
{
|
||||
return Operand >> (Count & 0x1f);
|
||||
}
|
||||
|
||||
INT32
|
||||
MulS32x32 (
|
||||
INT32 Value1,
|
||||
INT32 Value2,
|
||||
INT32 *ResultHigh
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Multiply two signed 32-bit numbers.
|
||||
|
||||
Arguments:
|
||||
|
||||
Value1 - first value to multiply
|
||||
Value2 - value to multiply Value1 by
|
||||
ResultHigh - overflow
|
||||
|
||||
Returns:
|
||||
|
||||
Value1 * Value2
|
||||
|
||||
Notes:
|
||||
|
||||
The 64-bit result is the concatenation of *ResultHigh and the return value
|
||||
|
||||
The product fits in 32 bits if
|
||||
(*ResultHigh == 0x00000000 AND *ResultLow_bit31 == 0)
|
||||
OR
|
||||
(*ResultHigh == 0xffffffff AND *ResultLow_bit31 == 1)
|
||||
|
||||
--*/
|
||||
{
|
||||
INT64 Rres64;
|
||||
INT32 Result;
|
||||
|
||||
Res64 = (INT64) Value1 * (INT64) Value2;
|
||||
*ResultHigh = (Res64 >> 32) & 0xffffffff;
|
||||
Result = Res64 & 0xffffffff;
|
||||
return Result;
|
||||
}
|
||||
|
||||
UINT32
|
||||
MulU32x32 (
|
||||
UINT32 Value1,
|
||||
UINT32 Value2,
|
||||
UINT32 *ResultHigh
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Multiply two unsigned 32-bit values.
|
||||
|
||||
Arguments:
|
||||
|
||||
Value1 - first number
|
||||
Value2 - number to multiply by Value1
|
||||
ResultHigh - overflow
|
||||
|
||||
Returns:
|
||||
|
||||
Value1 * Value2
|
||||
|
||||
Notes:
|
||||
|
||||
The 64-bit result is the concatenation of *ResultHigh and the return value.
|
||||
The product fits in 32 bits if *ResultHigh == 0x00000000
|
||||
|
||||
--*/
|
||||
{
|
||||
UINT64 Res64;
|
||||
UINT32 Result;
|
||||
|
||||
Res64 = (INT64) Value1 * (INT64) Value2;
|
||||
*ResultHigh = (Res64 >> 32) & 0xffffffff;
|
||||
Result = Res64 & 0xffffffff;
|
||||
return Result;
|
||||
}
|
||||
|
||||
INT32
|
||||
DivS32x32 (
|
||||
INT32 Value1,
|
||||
INT32 Value2,
|
||||
INT32 *Remainder,
|
||||
UINTN *error
|
||||
)
|
||||
//
|
||||
// signed 32-bit by signed 32-bit divide; the 32-bit remainder is
|
||||
// in *Remainder and the quotient is the return value; *error = 1 if the
|
||||
// divisor is 0, and it is 1 otherwise
|
||||
//
|
||||
{
|
||||
INT32 Result;
|
||||
|
||||
*error = 0;
|
||||
|
||||
if (Value2 == 0x0) {
|
||||
*error = 1;
|
||||
Result = 0x80000000;
|
||||
*Remainder = 0x80000000;
|
||||
} else {
|
||||
Result = Value1 / Value2;
|
||||
*Remainder = Value1 - Result * Value2;
|
||||
}
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
UINT32
|
||||
DivU32x32 (
|
||||
UINT32 Value1,
|
||||
UINT32 Value2,
|
||||
UINT32 *Remainder,
|
||||
UINTN *Error
|
||||
)
|
||||
//
|
||||
// unsigned 32-bit by unsigned 32-bit divide; the 32-bit remainder is
|
||||
// in *Remainder and the quotient is the return value; *error = 1 if the
|
||||
// divisor is 0, and it is 1 otherwise
|
||||
//
|
||||
{
|
||||
UINT32 Result;
|
||||
|
||||
*Error = 0;
|
||||
|
||||
if (Value2 == 0x0) {
|
||||
*Error = 1;
|
||||
Result = 0x80000000;
|
||||
*Remainder = 0x80000000;
|
||||
} else {
|
||||
Result = Value1 / Value2;
|
||||
*Remainder = Value1 - Result * Value2;
|
||||
}
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
INT64
|
||||
DivS64x64 (
|
||||
INT64 Value1,
|
||||
INT64 Value2,
|
||||
INT64 *Remainder,
|
||||
UINTN *Error
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Divide two 64-bit signed values.
|
||||
|
||||
Arguments:
|
||||
|
||||
Value1 - dividend
|
||||
Value2 - divisor
|
||||
Remainder - remainder of Value1/Value2
|
||||
Error - to flag errors (divide-by-0)
|
||||
|
||||
Returns:
|
||||
|
||||
Value1 / Valu2
|
||||
|
||||
Note:
|
||||
|
||||
The 64-bit remainder is in *Remainder and the quotient is the return value.
|
||||
*Error = 1 if the divisor is 0, and it is 1 otherwise
|
||||
|
||||
--*/
|
||||
{
|
||||
INT64 Result;
|
||||
|
||||
*Error = 0;
|
||||
|
||||
if (Value2 == 0x0) {
|
||||
*Error = 1;
|
||||
Result = 0x8000000000000000;
|
||||
*Remainder = 0x8000000000000000;
|
||||
} else {
|
||||
Result = Value1 / Value2;
|
||||
*Remainder = Value1 - Result * Value2;
|
||||
}
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
UINT64
|
||||
DivU64x64 (
|
||||
UINT64 Value1,
|
||||
UINT64 Value2,
|
||||
UINT64 *Remainder,
|
||||
UINTN *Error
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Divide two 64-bit unsigned values.
|
||||
|
||||
Arguments:
|
||||
|
||||
Value1 - dividend
|
||||
Value2 - divisor
|
||||
Remainder - remainder of Value1/Value2
|
||||
Error - to flag errors (divide-by-0)
|
||||
|
||||
Returns:
|
||||
|
||||
Value1 / Valu2
|
||||
|
||||
Note:
|
||||
|
||||
The 64-bit remainder is in *Remainder and the quotient is the return value.
|
||||
*Error = 1 if the divisor is 0, and it is 1 otherwise
|
||||
|
||||
--*/
|
||||
{
|
||||
UINT64 Result;
|
||||
|
||||
*Error = 0;
|
||||
|
||||
if (Value2 == 0x0) {
|
||||
*Error = 1;
|
||||
Result = 0x8000000000000000;
|
||||
*Remainder = 0x8000000000000000;
|
||||
} else {
|
||||
Result = Value1 / Value2;
|
||||
*Remainder = Value1 - Result * Value2;
|
||||
}
|
||||
|
||||
return Result;
|
||||
}
|
||||
@@ -1,144 +0,0 @@
|
||||
///*++
|
||||
//
|
||||
// Copyright (c) 2006, Intel Corporation
|
||||
// All rights reserved. This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//Module Name:
|
||||
//
|
||||
// IpfMul.s
|
||||
//
|
||||
//Abstract:
|
||||
//
|
||||
// Low level routines for IPF multiply support
|
||||
//
|
||||
//--*/
|
||||
|
||||
.file "IpfMul.s"
|
||||
.section .text
|
||||
|
||||
.proc MulS64x64#
|
||||
.align 32
|
||||
.globl MulS64x64#
|
||||
.align 32
|
||||
|
||||
///*++
|
||||
//
|
||||
//Routine Description:
|
||||
//
|
||||
// Multiply two 64-bit signed numbers.
|
||||
//
|
||||
//
|
||||
//Arguments:
|
||||
//
|
||||
// INT64
|
||||
// MulS64x64 (
|
||||
// IN INT64 Value1,
|
||||
// IN INT64 Value2,
|
||||
// OUT INT64 *ResultHigh);
|
||||
//
|
||||
//Returns:
|
||||
//
|
||||
// 64-bit signed result
|
||||
//
|
||||
//--*/
|
||||
|
||||
MulS64x64:
|
||||
// signed 64x64->128-bit multiply
|
||||
// A in r32, B in r33, Q_hi stored in [r34], Q_lo returned in r8
|
||||
{ .mfi
|
||||
alloc r31=ar.pfs,3,0,0,0 // r32-r34
|
||||
nop.f 0
|
||||
nop.i 0;;
|
||||
}
|
||||
{.mmi
|
||||
setf.sig f6=r32
|
||||
setf.sig f7=r33
|
||||
nop.i 0;;
|
||||
}
|
||||
|
||||
{.mfi
|
||||
nop.m 0
|
||||
xma.h f8=f6,f7,f0
|
||||
nop.i 0
|
||||
}
|
||||
{.mfi
|
||||
nop.m 0
|
||||
xma.l f6=f6,f7,f0
|
||||
nop.i 0;;
|
||||
}
|
||||
|
||||
|
||||
{.mmb
|
||||
stf8 [r34]=f8
|
||||
getf.sig r8=f6
|
||||
br.ret.sptk b0;;
|
||||
}
|
||||
|
||||
.endp MulS64x64
|
||||
|
||||
.proc MulU64x64#
|
||||
.align 32
|
||||
.globl MulU64x64#
|
||||
.align 32
|
||||
|
||||
|
||||
///*++
|
||||
//
|
||||
//Routine Description:
|
||||
//
|
||||
// Multiply two 64-bit unsigned numbers.
|
||||
//
|
||||
//
|
||||
//Arguments:
|
||||
//
|
||||
// UINT64
|
||||
// MulU64x64 (
|
||||
// IN UINT64 Value1,
|
||||
// IN UINT64 Value2,
|
||||
// OUT UINT64 *ResultHigh);
|
||||
//
|
||||
//Returns:
|
||||
//
|
||||
// 64-bit unsigned result
|
||||
//
|
||||
//--*/
|
||||
MulU64x64:
|
||||
// A in r32, B in r33, Q_hi stored in [r34], Q_lo returned in r8
|
||||
{ .mfi
|
||||
alloc r31=ar.pfs,3,0,0,0 // r32-r34
|
||||
nop.f 0
|
||||
nop.i 0;;
|
||||
}
|
||||
{.mmi
|
||||
setf.sig f6=r32
|
||||
setf.sig f7=r33
|
||||
nop.i 0;;
|
||||
}
|
||||
|
||||
{.mfi
|
||||
nop.m 0
|
||||
xma.hu f8=f6,f7,f0
|
||||
nop.i 0
|
||||
}
|
||||
{.mfi
|
||||
nop.m 0
|
||||
xma.l f6=f6,f7,f0
|
||||
nop.i 0;;
|
||||
}
|
||||
|
||||
|
||||
{.mmb
|
||||
stf8 [r34]=f8
|
||||
getf.sig r8=f6
|
||||
br.ret.sptk b0;;
|
||||
}
|
||||
|
||||
.endp MulU64x64
|
||||
|
||||
|
||||
Reference in New Issue
Block a user