Ported the EBC driver to use the MDE Base Math lib functions. Removed math functions from EBC driver. Need to check to see if MDE Math lib ASSERT behavior will cause any issues with EBC driver?
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1814 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -339,14 +339,14 @@ Returns:
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UINT8 *Ptr;
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UINT8 *ThunkBase;
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UINT64 Addr;
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UINT64 Code[3]; // Code in a bundle
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UINT64 RegNum; // register number for MOVL
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UINT64 I; // bits of MOVL immediate data
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UINT64 Ic; // bits of MOVL immediate data
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UINT64 Imm5c; // bits of MOVL immediate data
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UINT64 Imm9d; // bits of MOVL immediate data
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UINT64 Imm7b; // bits of MOVL immediate data
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UINT64 Br; // branch register for loading and jumping
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UINT64 Code[3]; // Code in a bundle
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UINT64 RegNum; // register number for MOVL
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UINT64 I; // bits of MOVL immediate data
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UINT64 Ic; // bits of MOVL immediate data
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UINT64 Imm5c; // bits of MOVL immediate data
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UINT64 Imm9d; // bits of MOVL immediate data
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UINT64 Imm7b; // bits of MOVL immediate data
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UINT64 Br; // branch register for loading and jumping
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UINT64 *Data64Ptr;
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UINT32 ThunkSize;
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UINT32 Size;
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@@ -441,25 +441,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -474,14 +474,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64 (Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64 (Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -506,25 +506,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -539,14 +539,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64 (Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64 (Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -578,25 +578,25 @@ Returns:
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//
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// Next is simply Addr[62:22] (41 bits) of the address
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//
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Code[1] = RightShiftU64 (Addr, 22) & 0x1ffffffffff;
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Code[1] = RShiftU64 (Addr, 22) & 0x1ffffffffff;
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//
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// Extract bits from the address for insertion into the instruction
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// i = Addr[63:63]
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//
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I = RightShiftU64 (Addr, 63) & 0x01;
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I = RShiftU64 (Addr, 63) & 0x01;
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//
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// ic = Addr[21:21]
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//
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Ic = RightShiftU64 (Addr, 21) & 0x01;
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Ic = RShiftU64 (Addr, 21) & 0x01;
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//
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// imm5c = Addr[20:16] for 5 bits
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//
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Imm5c = RightShiftU64 (Addr, 16) & 0x1F;
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Imm5c = RShiftU64 (Addr, 16) & 0x1F;
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//
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// imm9d = Addr[15:7] for 9 bits
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//
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Imm9d = RightShiftU64 (Addr, 7) & 0x1FF;
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Imm9d = RShiftU64 (Addr, 7) & 0x1FF;
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//
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// imm7b = Addr[6:0] for 7 bits
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//
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@@ -610,14 +610,14 @@ Returns:
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//
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// Next is jumbled data, including opcode and rest of address
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//
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Code[2] = LeftShiftU64(Imm7b, 13)
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| LeftShiftU64 (0x00, 20) // vc
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| LeftShiftU64 (Ic, 21)
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| LeftShiftU64 (Imm5c, 22)
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| LeftShiftU64 (Imm9d, 27)
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| LeftShiftU64 (I, 36)
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| LeftShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LeftShiftU64 ((RegNum & 0x7F), 6);
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Code[2] = LShiftU64(Imm7b, 13)
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| LShiftU64 (0x00, 20) // vc
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| LShiftU64 (Ic, 21)
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| LShiftU64 (Imm5c, 22)
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| LShiftU64 (Imm9d, 27)
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| LShiftU64 (I, 36)
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| LShiftU64 ((UINT64)MOVL_OPCODE, 37)
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| LShiftU64 ((RegNum & 0x7F), 6);
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WriteBundle ((VOID *) Ptr, 0x05, Code[0], Code[1], Code[2]);
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@@ -641,8 +641,8 @@ Returns:
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// register and user register (same user register as previous bundle).
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//
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Br = 6;
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Code[2] |= LeftShiftU64 (Br, 6);
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Code[2] |= LeftShiftU64 (RegNum, 13);
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Code[2] |= LShiftU64 (Br, 6);
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Code[2] |= LShiftU64 (RegNum, 13);
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WriteBundle ((VOID *) Ptr, 0x0d, Code[0], Code[1], Code[2]);
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//
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@@ -657,7 +657,7 @@ Returns:
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Code[0] = OPCODE_NOP;
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Code[1] = OPCODE_NOP;
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Code[2] = OPCODE_BR_COND_SPTK_FEW;
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Code[2] |= LeftShiftU64 (Br, 13);
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Code[2] |= LShiftU64 (Br, 13);
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WriteBundle ((VOID *) Ptr, 0x1d, Code[0], Code[1], Code[2]);
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//
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@@ -728,8 +728,8 @@ Returns:
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return EFI_INVALID_PARAMETER;
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}
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Low64 = LeftShiftU64 (Slot1, 46) | LeftShiftU64 (Slot0, 5) | Template;
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High64 = RightShiftU64 (Slot1, 18) | LeftShiftU64 (Slot2, 23);
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Low64 = LShiftU64 (Slot1, 46) | LShiftU64 (Slot0, 5) | Template;
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High64 = RShiftU64 (Slot1, 18) | LShiftU64 (Slot2, 23);
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//
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// Now write it all out
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@@ -737,13 +737,13 @@ Returns:
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BPtr = (UINT8 *) MemPtr;
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for (Index = 0; Index < 8; Index++) {
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*BPtr = (UINT8) Low64;
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Low64 = RightShiftU64 (Low64, 8);
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Low64 = RShiftU64 (Low64, 8);
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BPtr++;
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}
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for (Index = 0; Index < 8; Index++) {
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*BPtr = (UINT8) High64;
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High64 = RightShiftU64 (High64, 8);
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High64 = RShiftU64 (High64, 8);
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BPtr++;
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}
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@@ -814,21 +814,21 @@ Returns:
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goto Action;
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}
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CodeOne18 = RightShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;
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CodeOne18 = RShiftU64 (*((UINT64 *)CalleeAddr + 2), 46) & 0x3FFFF;
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CodeOne23 = (*((UINT64 *)CalleeAddr + 3)) & 0x7FFFFF;
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CodeTwoI = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;
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CodeTwoIc = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;
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CodeTwo7b = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;
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CodeTwo5c = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;
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CodeTwo9d = RightShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;
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CodeTwoI = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 59) & 0x1;
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CodeTwoIc = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 44) & 0x1;
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CodeTwo7b = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 36) & 0x7F;
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CodeTwo5c = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 45) & 0x1F;
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CodeTwo9d = RShiftU64 (*((UINT64 *)CalleeAddr + 3), 50) & 0x1FF;
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TargetEbcAddr = CodeTwo7b
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| LeftShiftU64 (CodeTwo9d, 7)
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| LeftShiftU64 (CodeTwo5c, 16)
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| LeftShiftU64 (CodeTwoIc, 21)
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| LeftShiftU64 (CodeOne18, 22)
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| LeftShiftU64 (CodeOne23, 40)
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| LeftShiftU64 (CodeTwoI, 63)
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| LShiftU64 (CodeTwo9d, 7)
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| LShiftU64 (CodeTwo5c, 16)
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| LShiftU64 (CodeTwoIc, 21)
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| LShiftU64 (CodeOne18, 22)
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| LShiftU64 (CodeOne23, 40)
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| LShiftU64 (CodeTwoI, 63)
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;
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Action:
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