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@@ -21,6 +21,8 @@
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/EdidDiscovered.h>
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#include <Protocol/EdidActive.h>
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#include <ArmPlatform.h>
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@@ -41,94 +43,119 @@ typedef struct {
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LCD_RESOLUTION mResolutions[] = {
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{ // Mode 0 : VGA : 640 x 480 x 24 bpp
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
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SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
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SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
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SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
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},
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{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
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UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
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UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
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UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
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},
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{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
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HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
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HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
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HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
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},
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{ // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 9 : VGA : 640 x 480 x 15 bpp
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 10 : SVGA : 800 x 600 x 15 bpp
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 11 : XGA : 1024 x 768 x 15 bpp
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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}
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{ // Mode 0 : VGA : 640 x 480 x 24 bpp
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
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SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
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SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
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SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
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},
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{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
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UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
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UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
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UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
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},
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{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
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HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
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HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
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HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
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},
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{ // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 9 : VGA : 640 x 480 x 15 bpp
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 10 : SVGA : 800 x 600 x 15 bpp
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 11 : XGA : 1024 x 768 x 15 bpp
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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},
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{ // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)
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VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,
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VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
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VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
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},
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{ // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)
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SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,
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SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
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SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
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},
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{ // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)
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XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,
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XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
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XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
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}
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};
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EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
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0,
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NULL
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};
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EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
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0,
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NULL
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};
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EFI_STATUS
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LcdPlatformInitializeDisplay (
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VOID
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) {
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IN EFI_HANDLE Handle
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)
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{
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EFI_STATUS Status;
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// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
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return ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);
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Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);
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if (!EFI_ERROR(Status)) {
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// Install the EDID Protocols
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Status = gBS->InstallMultipleProtocolInterfaces(
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&Handle,
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&gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
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&gEfiEdidActiveProtocolGuid, &mEdidActive,
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NULL
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);
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}
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return Status;
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}
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EFI_STATUS
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