ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory

Given that these days, our ARM port only supports ARMv7 and later, we
can assume that the page table walker's memory accesses are cache
coherent, and so there is no need to perform cache maintenance. It
does require the page tables themselves to reside in memory mapped as
writeback cacheable so ASSERT() that this is the case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

@@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress)
 //  IN VOID  *MVA                    // R1
 //  );
 ASM_FUNC(ArmUpdateTranslationTableEntry)
-  mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
-  dsb
   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
   dsb