MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource
The bug was caused by 728d74973c
"MdeModulePkg/PciBus: Count multiple hotplug resource paddings".
The patch firstly updated the Bridge->Alignment to the maximum
alignment of all devices under the bridge, then aligned the
Bridge->Length to Bridge->Alignment.
It caused too much resources were claimed.
The new patch firstly aligns Bridge->Length to Bridge->Alignment,
then updates the Bridge->Alignment to the maximum alignment of all
devices under the bridge.
Because the step to update the Bridge->Alignment is to make sure
the resource allocated to the bus under the Bridge meets all
devices alignment. But the Bridge->Length doesn't have to align
to the maximum alignment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
@@ -389,18 +389,7 @@ CalculateResourceAperture (
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//
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//
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// Adjust the bridge's alignment to the MAX (first) alignment of all children.
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// Adjust the aperture with the bridge's alignment
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//
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CurrentLink = Bridge->ChildList.ForwardLink;
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if (CurrentLink != &Bridge->ChildList) {
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Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
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if (Node->Alignment > Bridge->Alignment) {
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Bridge->Alignment = Node->Alignment;
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}
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}
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//
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// At last, adjust the aperture with the bridge's alignment
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//
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//
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Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);
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Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1);
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Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);
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Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1);
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@@ -410,6 +399,17 @@ CalculateResourceAperture (
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// Use the larger one between the padding resource and actual occupied resource.
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// Use the larger one between the padding resource and actual occupied resource.
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//
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//
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Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);
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Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]);
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//
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// Adjust the bridge's alignment to the MAX (first) alignment of all children.
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//
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CurrentLink = Bridge->ChildList.ForwardLink;
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if (CurrentLink != &Bridge->ChildList) {
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Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
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if (Node->Alignment > Bridge->Alignment) {
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Bridge->Alignment = Node->Alignment;
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}
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}
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}
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}
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/**
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/**
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