IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64. 2.Added FSPx_UPD_COMMON_FSP24 structures. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
@@ -1,7 +1,7 @@
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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@@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON
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.size:
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endstruc
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struc FSPM_UPD_COMMON_FSP24
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; FSP_UPD_HEADER {
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.FspUpdHeader: resd 8
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; }
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; FSPM_ARCH2_UPD {
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.Revision: resb 1
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.Reserved: resb 3
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.Length resd 1
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.StackBase: resq 1
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.StackSize: resq 1
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.BootLoaderTolumSize: resd 1
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.BootMode: resd 1
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.FspEventHandler resq 1
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.Reserved1: resb 24
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; }
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.size:
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endstruc
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;
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; Following functions will be provided in C
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;
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@@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue):
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pop eax
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FspStackSetup:
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mov ecx, [edx + FSPM_UPD_COMMON.Revision]
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cmp ecx, 3
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jae FspmUpdCommon2
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;
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; StackBase = temp memory base, StackSize = temp memory size
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;
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mov edi, [edx + FSPM_UPD_COMMON.StackBase]
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mov ecx, [edx + FSPM_UPD_COMMON.StackSize]
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jmp ChkFspHeapSize
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FspmUpdCommon2:
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mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
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mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
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ChkFspHeapSize:
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;
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; Keep using bootloader stack if heap size % is 0
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;
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@@ -219,7 +247,7 @@ exit:
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global ASM_PFX(FspPeiCoreEntryOff)
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ASM_PFX(FspPeiCoreEntryOff):
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;
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; This value will be pached by the build script
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; This value will be patched by the build script
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;
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DD 0x12345678
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@@ -1,7 +1,7 @@
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
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.FspUpdHeaderRevision: resb 1
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.FspUpdHeaderReserved: resb 23
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; }
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; FSPT_ARCH_UPD{
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.FsptArchUpd: resd 8
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; FSPT_ARCH_UPD {
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.FsptArchRevision: resb 1
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.FsptArchReserved: resb 3
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.FsptArchUpd: resd 7
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; }
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; FSPT_CORE_UPD {
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.MicrocodeCodeAddr: resd 1
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@@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22
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.size:
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endstruc
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struc LoadMicrocodeParamsFsp24
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; FSP_UPD_HEADER {
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.FspUpdHeaderSignature: resd 2
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.FspUpdHeaderRevision: resb 1
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.FspUpdHeaderReserved: resb 23
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; }
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; FSPT_ARCH2_UPD {
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.FsptArchRevision: resb 1
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.FsptArchReserved: resb 3
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.FsptArchLength: resd 1
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.FspDebugHandler resq 1
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.FsptArchUpd: resd 4
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; }
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; FSPT_CORE_UPD {
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.MicrocodeCodeAddr: resq 1
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.MicrocodeCodeSize: resq 1
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.CodeRegionBase: resq 1
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.CodeRegionSize: resq 1
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; }
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.size:
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endstruc
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;
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; Define SSE macros
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;
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@@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault):
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; Executed by SBSP and NBSP
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; Beginning of microcode update region starts on paragraph boundary
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;
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;
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; Save return address to EBP
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;
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movd ebp, mm7
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cmp esp, 0
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@@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault):
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; and report error if size is less than 2k
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; first check UPD header revision
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cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader
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jb Fsp20UpdHeader
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cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
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je Fsp24UpdHeader
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jmp Fsp22UpdHeader
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Fsp20UpdHeader:
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; UPD structure is compliant with FSP spec 2.0/2.1
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mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
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cmp eax, 0
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@@ -213,6 +241,19 @@ Fsp22UpdHeader:
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mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
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cmp esi, 0
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jnz CheckMainHeader
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jmp ParamError
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Fsp24UpdHeader:
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; UPD structure is compliant with FSP spec 2.4
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mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
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cmp eax, 0
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jz Exit2
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cmp eax, 0800h
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jl ParamError
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mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
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cmp esi, 0
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jnz CheckMainHeader
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ParamError:
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mov eax, 080000002h
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@@ -308,9 +349,13 @@ AdvanceFixedSize:
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CheckAddress:
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; Check UPD header revision
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cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader1
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cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jb Fsp20UpdHeader1
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cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
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je Fsp24UpdHeader1;
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jmp Fsp22UpdHeader1
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Fsp20UpdHeader1:
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; UPD structure is compliant with FSP spec 2.0/2.1
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; Is automatic size detection ?
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mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
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@@ -336,6 +381,19 @@ Fsp22UpdHeader1:
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jae Done ;Jif address is outside of microcode region
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jmp CheckMainHeader
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Fsp24UpdHeader1:
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; UPD structure is compliant with FSP spec 2.4
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; Is automatic size detection ?
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mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
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cmp eax, 0ffffffffh
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jz LoadMicrocodeDefault4
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; Address >= microcode region address + microcode region size?
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add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
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cmp esi, eax
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jae Done ;Jif address is outside of microcode region
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jmp CheckMainHeader
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LoadMicrocodeDefault4:
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; Is valid Microcode start point ?
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cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
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@@ -351,7 +409,7 @@ LoadCheck:
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mov eax, 1
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cpuid
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mov ecx, MSR_IA32_BIOS_SIGN_ID
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rdmsr ; Get current microcode signature
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rdmsr ; Get current microcode signature
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; Verify this microcode update is not already loaded
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cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
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@@ -405,8 +463,12 @@ ASM_PFX(EstablishStackFsp):
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; check UPD structure revision (edx + 8)
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cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
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jae Fsp22UpdHeader2
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jb Fsp20UpdHeader2
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cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
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je Fsp24UpdHeader2
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jmp Fsp22UpdHeader2
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Fsp20UpdHeader2:
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; UPD structure is compliant with FSP spec 2.0/2.1
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push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12
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push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
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@@ -420,6 +482,14 @@ Fsp22UpdHeader2:
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push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8
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push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4
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push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
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jmp ContinueAfterUpdPush
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Fsp24UpdHeader2:
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; UPD structure is compliant with FSP spec 2.4
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push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24
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push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16
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push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8
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push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0
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ContinueAfterUpdPush:
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;
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@@ -517,13 +587,13 @@ ASM_PFX(TempRamInitApi):
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cmp eax, 0
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jnz TempRamInitExit
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LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
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LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
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TempRamInitExit:
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mov bl, al ; save al data in bl
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mov al, 07Fh ; API exit postcode 7f
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out 080h, al
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mov al, bl ; restore al data from bl
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mov bl, al ; save al data in bl
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mov al, 07Fh ; API exit postcode 7f
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out 080h, al
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mov al, bl ; restore al data from bl
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;
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; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
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