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Vlv2TbltDevicePkg: Sync the branch changes to trunk.

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Support compatible board, and fixed some bugs. 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tim He <tim.he@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18149 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Tim He
2015-08-04 02:55:02 +00:00
committed by timhe
parent c5d5379937
commit 6f2ef18e80
23 changed files with 215 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c
View File

@@ -370,6 +370,7 @@ ConfigurePlatformClocks (
if(!EFI_ERROR (Status)){
EnableSpreadSpectrum = SystemConfiguration.EnableClockSpreadSpec;
}
//
// Perform platform-specific intialization dependent upon Board ID:
//

5
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c
View File

@@ -150,7 +150,7 @@ MultiPlatformGpioTableInit (
EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
UINTN VarSize;
SYSTEM_CONFIGURATION SystemConfiguration;
DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));
//
@@ -509,6 +509,7 @@ MultiPlatformGpioProgram (
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);
//
// GPIO Wake Enable.
//
IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);
@@ -523,7 +524,7 @@ MultiPlatformGpioProgram (
InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);
InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);
break;
default:
default:
break;
}

12
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h
View File

@@ -46,33 +46,33 @@ GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,TRISTS ,NA ,F0
GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,TRISTS ,NA ,F0 , , ,NONE ,0x6a),
GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,TRISTS ,NA ,F0 , , ,NONE ,0x68),
};
//
// Minnow2
//
#define MINNOW2_GPIO_USE_SEL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_USE_SEL_VAL_SUS2 0x00000001
#define MINNOW2_GPIO_IO_SEL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_IO_SEL_VAL_SUS2 0x00000001
#define MINNOW2_GPIO_LVL_VAL_0_31 0x00000000
#define MINNOW2_GPIO_LVL_VAL_32_63 0x00000000
#define MINNOW2_GPIO_LVL_VAL_64_70 0x00000000
#define MINNOW2_GPIO_LVL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_LVL_VAL_SUS 0x00000000
#define MINNOW2_GPIO_LVL_VAL_SUS2 0x00000001
#define MINNOW2_GPIO_TPE_VAL_0_31 0x00000000
#define MINNOW2_GPIO_TPE_VAL_SUS 0x00000000
#define MINNOW2_GPIO_TPE_VAL_SUS 0x00000000
#define MINNOW2_GPIO_TPE_VAL_SUS2 0x00000001
#define MINNOW2_GPIO_TNE_VAL_0_31 0x00000000

1
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c
View File

@@ -34,6 +34,7 @@ InitializeBoardOemId (
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
UINT64 OemId;
UINT64 OemTableId;
//

7
Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c
View File

@@ -32,9 +32,10 @@ InitializeBoardSsidSvid (
InitializeBoardSsidSvid (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
UINT32 SsidSvidValue = 0;
)
{
UINT32 SsidSvidValue = 0;
//
// Set OEM ID according to Board ID.
//