UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.
PiSmmCpuDxeSmm consumes SmmAttributesTable and setup page table: 1) Code region is marked as read-only and Data region is non-executable, if the PE image is 4K aligned. 2) Important data structure is set to RO, such as GDT/IDT. 3) SmmSaveState is set to non-executable, and SmmEntrypoint is set to read-only. 4) If static page is supported, page table is read-only. We use page table to protect other components, and itself. If we use dynamic paging, we can still provide *partial* protection. And hope page table is not modified by other components. The XD enabling code is moved to SmiEntry to let NX take effect. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
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@@ -1,7 +1,7 @@
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/** @file
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X64 processor specific functions to enable SMM profile.
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Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -45,12 +45,13 @@ InitSmmS3Cr3 (
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//
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// Generate PAE page table for the first 4GB memory space
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//
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Pages = Gen4GPageTable (1, FALSE);
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Pages = Gen4GPageTable (FALSE);
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//
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// Fill Page-Table-Level4 (PML4) entry
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//
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PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));
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PTEntry = (UINT64*)AllocatePageTableMemory (1);
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ASSERT (PTEntry != NULL);
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*PTEntry = Pages | PAGE_ATTRIBUTE_BITS;
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ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
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