From 7285f275ff5482fb8cbf1ce5f4cd2e4df0a3cc62 Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Tue, 28 Jan 2020 01:52:45 +0800 Subject: [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready Before writing data to FIFO, wait for the serial port to be ready, to make sure both the transmit FIFO and shift register empty. Code comment was saying the right thing but code was missing a check. Reviewed-by: Zhichao Gao Signed-off-by: Ashish Singhal --- .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index bbae379887..9cb50dd80d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -646,7 +646,7 @@ SerialPortWrite ( // Wait for the serial port to be ready, to make sure both the transmit FIFO // and shift register empty. // - while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0); + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)); // // Fill then entire Tx FIFO