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UefiCpuPkg: Clean up source files

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:14:20 +08:00
parent 77695f4da3
commit 7367cc6c24
59 changed files with 614 additions and 614 deletions
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6
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
View File

@@ -8,10 +8,10 @@
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
@@ -21,7 +21,7 @@
FILE_GUID = 34C24FD7-7A90-45c2-89FD-946473D9CE98
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = UefiCpuLib
LIBRARY_CLASS = UefiCpuLib
#
# The following information is for reference only and not required by the build tools.

4
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
View File

@@ -3,13 +3,13 @@
//
// The library routines are UEFI specification compliant.
//
// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

12
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
@@ -13,7 +13,7 @@
#------------------------------------------------------------------------------
#
# Float control word initial value:
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
@@ -41,7 +41,7 @@ ASM_PFX(InitializeFloatingPointUnits):
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
@@ -50,14 +50,14 @@ ASM_PFX(InitializeFloatingPointUnits):
cpuid
btl $25, %edx
jnc Done
#
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
movl %cr4, %eax
or $0x200, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction

16
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
@@ -27,31 +27,31 @@ ASM_PFX(InitializeFloatingPointUnits):
# Initialize floating point units
#
finit
#
# Float control word initial value:
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
pushq $0x037F
lea (%rsp), %rax
lea (%rsp), %rax
fldcw (%rax)
popq %rax
#
# Set OSFXSR bit 9 in CR4
#
movq %cr4, %rax
movq %cr4, %rax
or $0x200, %rax
movq %rax, %cr4
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
#
pushq $0x01F80
lea (%rsp), %rax
ldmxcsr (%rax)
popq %rax
ret

64
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@@ -3,7 +3,7 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
This program and the accompanying materials
@@ -68,12 +68,12 @@ LocalApicBaseAddressMsrSupported (
{
UINT32 RegEax;
UINTN FamilyId;
AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
@@ -104,7 +104,7 @@ GetLocalApicBaseAddress (
}
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
@@ -197,7 +197,7 @@ WriteLocalApicReg (
/**
Send an IPI by writing to ICR.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param IcrLow 32-bit value to be written to the low half of ICR.
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
@@ -275,7 +275,7 @@ GetApicMode (
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
//
// Check to see if the CPU supports the APIC Base Address MSR
// Check to see if the CPU supports the APIC Base Address MSR
//
if (LocalApicBaseAddressMsrSupported ()) {
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
@@ -315,7 +315,7 @@ SetApicMode (
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
the 32-bit local APIC ID is returned as initial APIC ID.
@return 32-bit initial local APIC ID of the executing processor.
@@ -338,7 +338,7 @@ GetInitialApicId (
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
//
// If CPUID Leaf B is supported,
// If CPUID Leaf B is supported,
// And CPUID.0BH:EBX[15:0] reports a non-zero value,
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
@@ -368,7 +368,7 @@ GetApicId (
UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
if ((ApicId = GetInitialApicId ()) < 0x100) {
//
// If the initial local APIC ID is less 0x100, read APIC ID from
@@ -397,7 +397,7 @@ GetApicVersion (
/**
Send a Fixed IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId The local APIC ID of the target processor.
@param Vector The vector number of the interrupt being sent.
@@ -421,7 +421,7 @@ SendFixedIpi (
/**
Send a Fixed IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
@param Vector The vector number of the interrupt being sent.
**/
@@ -444,7 +444,7 @@ SendFixedIpiAllExcludingSelf (
/**
Send a SMI IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
@@ -465,7 +465,7 @@ SendSmiIpi (
/**
Send a SMI IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
@@ -485,7 +485,7 @@ SendSmiIpiAllExcludingSelf (
/**
Send an INIT IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
@@ -506,7 +506,7 @@ SendInitIpi (
/**
Send an INIT IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
@@ -526,7 +526,7 @@ SendInitIpiAllExcludingSelf (
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@@ -563,7 +563,7 @@ SendInitSipiSipi (
/**
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@@ -767,7 +767,7 @@ InitializeApicTimer (
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
}
//
@@ -897,13 +897,13 @@ SendApicEoi (
}
/**
Get the 32-bit address that a device should use to send a Message Signaled
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
EFIAPI
GetApicMsiAddress (
VOID
)
@@ -911,7 +911,7 @@ GetApicMsiAddress (
LOCAL_APIC_MSI_ADDRESS MsiAddress;
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
@@ -919,17 +919,17 @@ GetApicMsiAddress (
MsiAddress.Bits.DestinationId = GetApicId ();
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
@@ -937,19 +937,19 @@ GetApicMsiAddress (
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
@@ -961,7 +961,7 @@ GetApicMsiValue (
ASSERT (Vector >= 0x10 && Vector <= 0xFE);
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
MsiData.Uint64 = 0;
MsiData.Bits.Vector = Vector;
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;

8
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
View File

@@ -4,15 +4,15 @@
# Note: Local APIC library assumes local APIC is enabled. It does not handle cases
# where local APIC is disabled.
#
# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
@@ -22,7 +22,7 @@
FILE_GUID = D87CA0A8-1AC2-439b-90F8-EF4A2AC88DAF
MODULE_TYPE = BASE
VERSION_STRING = 1.1
LIBRARY_CLASS = LocalApicLib
LIBRARY_CLASS = LocalApicLib
#
# The following information is for reference only and not required by the build tools.

4
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.uni
View File

@@ -4,13 +4,13 @@
// Note: Local APIC library assumes local APIC is enabled. It does not handle cases
// where local APIC is disabled.
//
// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

62
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@@ -4,7 +4,7 @@
This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
This program and the accompanying materials
@@ -69,12 +69,12 @@ LocalApicBaseAddressMsrSupported (
{
UINT32 RegEax;
UINTN FamilyId;
AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
@@ -105,7 +105,7 @@ GetLocalApicBaseAddress (
}
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
@@ -236,7 +236,7 @@ WriteLocalApicReg (
/**
Send an IPI by writing to ICR.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param IcrLow 32-bit value to be written to the low half of ICR.
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
@@ -301,7 +301,7 @@ SendIpi (
} else {
//
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode.
//
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
@@ -414,7 +414,7 @@ SetApicMode (
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
the 32-bit local APIC ID is returned as initial APIC ID.
@return 32-bit initial local APIC ID of the executing processor.
@@ -435,7 +435,7 @@ GetInitialApicId (
//
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
//
// If CPUID Leaf B is supported,
// If CPUID Leaf B is supported,
// And CPUID.0BH:EBX[15:0] reports a non-zero value,
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
@@ -492,7 +492,7 @@ GetApicVersion (
/**
Send a Fixed IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId The local APIC ID of the target processor.
@param Vector The vector number of the interrupt being sent.
@@ -516,7 +516,7 @@ SendFixedIpi (
/**
Send a Fixed IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
@param Vector The vector number of the interrupt being sent.
**/
@@ -539,7 +539,7 @@ SendFixedIpiAllExcludingSelf (
/**
Send a SMI IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
@@ -560,7 +560,7 @@ SendSmiIpi (
/**
Send a SMI IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
@@ -580,7 +580,7 @@ SendSmiIpiAllExcludingSelf (
/**
Send an INIT IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
@@ -601,7 +601,7 @@ SendInitIpi (
/**
Send an INIT IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
**/
VOID
EFIAPI
@@ -621,7 +621,7 @@ SendInitIpiAllExcludingSelf (
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
This function returns after the IPI has been accepted by the target processor.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@@ -658,7 +658,7 @@ SendInitSipiSipi (
/**
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
This function returns after the IPI has been accepted by the target processors.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@@ -862,7 +862,7 @@ InitializeApicTimer (
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
}
//
@@ -992,13 +992,13 @@ SendApicEoi (
}
/**
Get the 32-bit address that a device should use to send a Message Signaled
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
EFIAPI
GetApicMsiAddress (
VOID
)
@@ -1006,7 +1006,7 @@ GetApicMsiAddress (
LOCAL_APIC_MSI_ADDRESS MsiAddress;
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
@@ -1014,17 +1014,17 @@ GetApicMsiAddress (
MsiAddress.Bits.DestinationId = GetApicId ();
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
@@ -1032,19 +1032,19 @@ GetApicMsiAddress (
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
@@ -1056,7 +1056,7 @@ GetApicMsiValue (
ASSERT (Vector >= 0x10 && Vector <= 0xFE);
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
MsiData.Uint64 = 0;
MsiData.Bits.Vector = Vector;
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;

8
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
View File

@@ -4,15 +4,15 @@
# Note: Local APIC library assumes local APIC is enabled. It does not handle cases
# where local APIC is disabled.
#
# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
@@ -22,7 +22,7 @@
FILE_GUID = 967B6E05-F10D-4c10-8BF7-365291CA143F
MODULE_TYPE = BASE
VERSION_STRING = 1.1
LIBRARY_CLASS = LocalApicLib
LIBRARY_CLASS = LocalApicLib
#
# The following information is for reference only and not required by the build tools.

4
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni
View File

@@ -4,13 +4,13 @@
// Note: Local APIC library assumes local APIC is enabled. It does not handle cases
// where local APIC is disabled.
//
// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

14
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
View File

@@ -1,7 +1,7 @@
/** @file
CPU Common features library header file.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -855,7 +855,7 @@ FeatureControlGetConfigData (
);
/**
Detects if Protected Processor Inventory Number feature supported on current
Detects if Protected Processor Inventory Number feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -889,14 +889,14 @@ PpinSupport (
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@param[in] State If TRUE, then the Protected Processor Inventory
@param[in] State If TRUE, then the Protected Processor Inventory
Number feature must be enabled.
If FALSE, then the Protected Processor Inventory
If FALSE, then the Protected Processor Inventory
Number feature must be disabled.
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
initialized.
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
locked.
**/
@@ -910,7 +910,7 @@ PpinInitialize (
);
/**
Detects if Local machine check exception feature supported on current
Detects if Local machine check exception feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.

4
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
View File

@@ -4,7 +4,7 @@
# This library registers CPU features defined in Intel(R) 64 and IA-32
# Architectures Software Developer's Manual.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -68,4 +68,4 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES

2
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
View File

@@ -235,7 +235,7 @@ McgCtlInitialize (
}
/**
Detects if Local machine check exception feature supported on current
Detects if Local machine check exception feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.

16
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
View File

@@ -1,7 +1,7 @@
/** @file
Protected Processor Inventory Number(PPIN) feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,7 +15,7 @@
#include "CpuCommonFeatures.h"
/**
Detects if Protected Processor Inventory Number feature supported on current
Detects if Protected Processor Inventory Number feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -41,13 +41,13 @@ PpinSupport (
{
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
if ((CpuInfo->DisplayFamily == 0x06) &&
if ((CpuInfo->DisplayFamily == 0x06) &&
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
(CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product
(CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) {
//
// Check whether platform support this feature.
@@ -69,14 +69,14 @@ PpinSupport (
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@param[in] State If TRUE, then the Protected Processor Inventory
@param[in] State If TRUE, then the Protected Processor Inventory
Number feature must be enabled.
If FALSE, then the Protected Processor Inventory
If FALSE, then the Protected Processor Inventory
Number feature must be disabled.
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
initialized.
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
locked.
**/

20
UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
View File

@@ -1,7 +1,7 @@
/** @file
Intel Processor Trace feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,11 +16,11 @@
///
/// This macro define the max entries in the Topa table.
/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
/// current table (for circular array) or to the base of another table.
/// At least 2 entries are needed because the list of entries must
/// be terminated by an entry with the END bit set to 1, so 2
/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
/// current table (for circular array) or to the base of another table.
/// At least 2 entries are needed because the list of entries must
/// be terminated by an entry with the END bit set to 1, so 2
/// entries are required to use a single valid entry.
///
#define MAX_TOPA_ENTRY_COUNT 2
@@ -43,7 +43,7 @@ typedef struct {
typedef struct {
UINT32 NumberOfProcessors;
UINT8 ProcTraceOutputScheme;
UINT8 ProcTraceOutputScheme;
UINT32 ProcTraceMemSize;
UINTN *ThreadMemRegionTable;
@@ -88,7 +88,7 @@ ProcTraceGetConfigData (
}
/**
Detects if Intel Processor Trace feature supported on current
Detects if Intel Processor Trace feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -291,7 +291,7 @@ ProcTraceInitialize (
//
// Single Range output scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
@@ -337,7 +337,7 @@ ProcTraceInitialize (
//
// ToPA(Table of physical address) scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
//
// Create ToPA structure aligned at 4KB for each logical thread

4
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
View File

@@ -1,7 +1,7 @@
/** @file
CPU Exception Handler Library common functions.
Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -177,4 +177,4 @@ ReadAndVerifyVectorInfo (
VectorInfo ++;
}
return EFI_SUCCESS;
}
}

6
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
View File

@@ -1,7 +1,7 @@
/** @file
MP initialize support functions for DXE phase.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -268,7 +268,7 @@ RelocateApLoop (
ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc;
UINTN ProcessorNumber;
MpInitLibWhoAmI (&ProcessorNumber);
MpInitLibWhoAmI (&ProcessorNumber);
CpuMpData = GetCpuMpData ();
MwaitSupport = IsMwaitSupport ();
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;
@@ -406,7 +406,7 @@ InitMpGlobalData (
//
// Make sure that the buffer memory is executable if NX protection is enabled
// for EfiReservedMemoryType.
//
//
// TODO: Check EFI_MEMORY_XP bit set or not once it's available in DXE GCD
// service.
//

4
UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
View File

@@ -193,11 +193,11 @@ GetNextProcNumber:
jz ProgramStack
add edi, 20
inc ebx
jmp GetNextProcNumber
jmp GetNextProcNumber
ProgramStack:
mov esp, [edi + 12]
CProcedureInvoke:
push ebp ; push BIST data at top of AP stack
xor ebp, ebp ; clear ebp for call stack trace

6
UefiCpuPkg/Library/MpInitLib/MpLib.c
View File

@@ -655,7 +655,7 @@ ApWakeupFunction (
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);
//
// Enable source debugging on AP function
//
//
EnableDebugAgent ();
//
// Invoke AP function here
@@ -1115,7 +1115,7 @@ CalculateTimeout (
//
// GetPerformanceCounterProperties () returns the timestamp counter's frequency
// in Hz.
// in Hz.
//
TimestampCounterFreq = GetPerformanceCounterProperties (NULL, NULL);
@@ -1737,7 +1737,7 @@ MpInitLibGetProcessorInfo (
enabled AP. Otherwise, it will be disabled.
@retval EFI_SUCCESS BSP successfully switched.
@retval others Failed to switch BSP.
@retval others Failed to switch BSP.
**/
EFI_STATUS

4
UefiCpuPkg/Library/MpInitLib/MpLib.h
View File

@@ -1,7 +1,7 @@
/** @file
Common header file for MP Initialize Library.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -463,7 +463,7 @@ StartupThisAPWorker (
enabled AP. Otherwise, it will be disabled.
@retval EFI_SUCCESS BSP successfully switched.
@retval others Failed to switch BSP.
@retval others Failed to switch BSP.
**/
EFI_STATUS

2
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
View File

@@ -216,7 +216,7 @@ GetNextProcNumber:
jz ProgramStack
add edi, 20
inc ebx
jmp GetNextProcNumber
jmp GetNextProcNumber
ProgramStack:
mov rsp, qword [edi + 12]

8
UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
View File

@@ -1,15 +1,15 @@
## @file
# MTRR library provides APIs for MTRR operation.
#
# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
@@ -19,7 +19,7 @@
FILE_GUID = 6826b408-f4f3-47ee-917f-af7047f9d937
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = MtrrLib
LIBRARY_CLASS = MtrrLib
#

4
UefiCpuPkg/Library/MtrrLib/MtrrLib.uni
View File

@@ -3,13 +3,13 @@
//
// MTRR library provides APIs for MTRR operation.
//
// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

6
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
View File

@@ -1,7 +1,7 @@
/** @file
CPU Features Initialize functions.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -63,7 +63,7 @@ GetSupportPcd (
UINT8 *SupportBitMask;
SupportBitMask = AllocateCopyPool (
PcdGetSize (PcdCpuFeaturesSupport),
PcdGetSize (PcdCpuFeaturesSupport),
PcdGetPtr (PcdCpuFeaturesSupport)
);
ASSERT (SupportBitMask != NULL);
@@ -84,7 +84,7 @@ GetConfigurationPcd (
UINT8 *SupportBitMask;
SupportBitMask = AllocateCopyPool (
PcdGetSize (PcdCpuFeaturesUserConfiguration),
PcdGetSize (PcdCpuFeaturesUserConfiguration),
PcdGetPtr (PcdCpuFeaturesUserConfiguration)
);
ASSERT (SupportBitMask != NULL);

8
UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
View File

@@ -3,9 +3,9 @@
#
# Timer Library that only uses CPU resources to provide calibrated delays
# on IA-32, x64, and IPF.
# Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib
# in their initialization without any issues. They only have to be careful in
# the implementation of runtime services and SMI handlers.
# Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib
# in their initialization without any issues. They only have to be careful in
# the implementation of runtime services and SMI handlers.
# Because CPU Local APIC and ITC could be programmed by OS, it cannot be
# used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM
# drivers and runtime drivers.
@@ -13,7 +13,7 @@
# This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in
# that it uses the local APIC library so that it supports x2APIC mode.
#
# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License

4
UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.uni
View File

@@ -9,11 +9,11 @@
// Because CPU Local APIC and ITC could be programmed by OS, it cannot be
// used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM
// drivers and runtime drivers.
//
//
// This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in
// that it uses the local APIC library so that it supports x2APIC mode.
//
// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License

4
UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
View File

@@ -2,8 +2,8 @@
Timer Library functions built upon local APIC on IA32/x64.
This library uses the local APIC library so that it supports x2APIC mode.
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at