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UefiCpuPkg: Clean up source files

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1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:14:20 +08:00
parent 77695f4da3
commit 7367cc6c24
59 changed files with 614 additions and 614 deletions
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6
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
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@@ -8,10 +8,10 @@
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
@@ -21,7 +21,7 @@
FILE_GUID = 34C24FD7-7A90-45c2-89FD-946473D9CE98
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = UefiCpuLib
LIBRARY_CLASS = UefiCpuLib
#
# The following information is for reference only and not required by the build tools.

4
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
View File

@@ -3,13 +3,13 @@
//
// The library routines are UEFI specification compliant.
//
// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//

12
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
@@ -13,7 +13,7 @@
#------------------------------------------------------------------------------
#
# Float control word initial value:
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
@@ -41,7 +41,7 @@ ASM_PFX(InitializeFloatingPointUnits):
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
@@ -50,14 +50,14 @@ ASM_PFX(InitializeFloatingPointUnits):
cpuid
btl $25, %edx
jnc Done
#
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
movl %cr4, %eax
or $0x200, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction

16
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
View File

@@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
@@ -27,31 +27,31 @@ ASM_PFX(InitializeFloatingPointUnits):
# Initialize floating point units
#
finit
#
# Float control word initial value:
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
pushq $0x037F
lea (%rsp), %rax
lea (%rsp), %rax
fldcw (%rax)
popq %rax
#
# Set OSFXSR bit 9 in CR4
#
movq %cr4, %rax
movq %cr4, %rax
or $0x200, %rax
movq %rax, %cr4
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
#
pushq $0x01F80
lea (%rsp), %rax
ldmxcsr (%rax)
popq %rax
ret