UefiCpuPkg: Clean up source files
1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
@@ -3,7 +3,7 @@
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This local APIC library instance supports xAPIC mode only.
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Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
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This program and the accompanying materials
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@@ -68,12 +68,12 @@ LocalApicBaseAddressMsrSupported (
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{
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UINT32 RegEax;
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UINTN FamilyId;
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AsmCpuid (1, &RegEax, NULL, NULL, NULL);
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FamilyId = BitFieldRead32 (RegEax, 8, 11);
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if (FamilyId == 0x04 || FamilyId == 0x05) {
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//
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// CPUs with a FamilyId of 0x04 or 0x05 do not support the
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// CPUs with a FamilyId of 0x04 or 0x05 do not support the
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// Local APIC Base Address MSR
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//
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return FALSE;
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@@ -104,7 +104,7 @@ GetLocalApicBaseAddress (
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}
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
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(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
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}
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@@ -197,7 +197,7 @@ WriteLocalApicReg (
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/**
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Send an IPI by writing to ICR.
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This function returns after the IPI has been accepted by the target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param IcrLow 32-bit value to be written to the low half of ICR.
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@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
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@@ -275,7 +275,7 @@ GetApicMode (
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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//
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// Check to see if the CPU supports the APIC Base Address MSR
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// Check to see if the CPU supports the APIC Base Address MSR
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//
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if (LocalApicBaseAddressMsrSupported ()) {
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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@@ -315,7 +315,7 @@ SetApicMode (
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Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
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In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
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In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
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In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
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the 32-bit local APIC ID is returned as initial APIC ID.
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@return 32-bit initial local APIC ID of the executing processor.
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@@ -338,7 +338,7 @@ GetInitialApicId (
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AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
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//
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// If CPUID Leaf B is supported,
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// If CPUID Leaf B is supported,
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// And CPUID.0BH:EBX[15:0] reports a non-zero value,
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// Then the initial 32-bit APIC ID = CPUID.0BH:EDX
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// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
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@@ -368,7 +368,7 @@ GetApicId (
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UINT32 ApicId;
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ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
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if ((ApicId = GetInitialApicId ()) < 0x100) {
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//
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// If the initial local APIC ID is less 0x100, read APIC ID from
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@@ -397,7 +397,7 @@ GetApicVersion (
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/**
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Send a Fixed IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId The local APIC ID of the target processor.
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@param Vector The vector number of the interrupt being sent.
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@@ -421,7 +421,7 @@ SendFixedIpi (
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/**
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Send a Fixed IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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This function returns after the IPI has been accepted by the target processors.
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@param Vector The vector number of the interrupt being sent.
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**/
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@@ -444,7 +444,7 @@ SendFixedIpiAllExcludingSelf (
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/**
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Send a SMI IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId Specify the local APIC ID of the target processor.
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**/
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@@ -465,7 +465,7 @@ SendSmiIpi (
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/**
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Send a SMI IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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This function returns after the IPI has been accepted by the target processors.
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**/
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VOID
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EFIAPI
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@@ -485,7 +485,7 @@ SendSmiIpiAllExcludingSelf (
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/**
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Send an INIT IPI to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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This function returns after the IPI has been accepted by the target processor.
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@param ApicId Specify the local APIC ID of the target processor.
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**/
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@@ -506,7 +506,7 @@ SendInitIpi (
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/**
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Send an INIT IPI to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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This function returns after the IPI has been accepted by the target processors.
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**/
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VOID
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EFIAPI
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@@ -526,7 +526,7 @@ SendInitIpiAllExcludingSelf (
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/**
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Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
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This function returns after the IPI has been accepted by the target processor.
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This function returns after the IPI has been accepted by the target processor.
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if StartupRoutine >= 1M, then ASSERT.
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if StartupRoutine is not multiple of 4K, then ASSERT.
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@@ -563,7 +563,7 @@ SendInitSipiSipi (
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/**
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Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
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This function returns after the IPI has been accepted by the target processors.
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This function returns after the IPI has been accepted by the target processors.
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if StartupRoutine >= 1M, then ASSERT.
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if StartupRoutine is not multiple of 4K, then ASSERT.
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@@ -767,7 +767,7 @@ InitializeApicTimer (
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Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
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Dcr.Bits.DivideValue1 = (Divisor & 0x3);
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Dcr.Bits.DivideValue2 = (Divisor >> 2);
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WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
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WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
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}
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//
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@@ -897,13 +897,13 @@ SendApicEoi (
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}
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/**
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Get the 32-bit address that a device should use to send a Message Signaled
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Get the 32-bit address that a device should use to send a Message Signaled
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Interrupt (MSI) to the Local APIC of the currently executing processor.
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@return 32-bit address used to send an MSI to the Local APIC.
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**/
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UINT32
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EFIAPI
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EFIAPI
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GetApicMsiAddress (
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VOID
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)
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@@ -911,7 +911,7 @@ GetApicMsiAddress (
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LOCAL_APIC_MSI_ADDRESS MsiAddress;
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//
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// Return address for an MSI interrupt to be delivered only to the APIC ID
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// Return address for an MSI interrupt to be delivered only to the APIC ID
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// of the currently executing processor.
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//
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MsiAddress.Uint32 = 0;
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@@ -919,17 +919,17 @@ GetApicMsiAddress (
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MsiAddress.Bits.DestinationId = GetApicId ();
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return MsiAddress.Uint32;
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}
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/**
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Get the 64-bit data value that a device should use to send a Message Signaled
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Get the 64-bit data value that a device should use to send a Message Signaled
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Interrupt (MSI) to the Local APIC of the currently executing processor.
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If Vector is not in range 0x10..0xFE, then ASSERT().
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If DeliveryMode is not supported, then ASSERT().
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@param Vector The 8-bit interrupt vector associated with the MSI.
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@param Vector The 8-bit interrupt vector associated with the MSI.
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Must be in the range 0x10..0xFE
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@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
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@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
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is handled. The only supported values are:
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0: LOCAL_APIC_DELIVERY_MODE_FIXED
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1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
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@@ -937,19 +937,19 @@ GetApicMsiAddress (
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4: LOCAL_APIC_DELIVERY_MODE_NMI
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5: LOCAL_APIC_DELIVERY_MODE_INIT
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7: LOCAL_APIC_DELIVERY_MODE_EXTINT
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@param LevelTriggered TRUE specifies a level triggered interrupt.
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@param LevelTriggered TRUE specifies a level triggered interrupt.
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FALSE specifies an edge triggered interrupt.
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@param AssertionLevel Ignored if LevelTriggered is FALSE.
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TRUE specifies a level triggered interrupt that active
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TRUE specifies a level triggered interrupt that active
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when the interrupt line is asserted.
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FALSE specifies a level triggered interrupt that active
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FALSE specifies a level triggered interrupt that active
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when the interrupt line is deasserted.
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@return 64-bit data value used to send an MSI to the Local APIC.
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**/
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UINT64
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EFIAPI
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EFIAPI
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GetApicMsiValue (
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IN UINT8 Vector,
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IN UINTN DeliveryMode,
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@@ -961,7 +961,7 @@ GetApicMsiValue (
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ASSERT (Vector >= 0x10 && Vector <= 0xFE);
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ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
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MsiData.Uint64 = 0;
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MsiData.Bits.Vector = Vector;
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MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
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