UefiCpuPkg: Clean up source files
1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
@@ -1,7 +1,7 @@
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/** @file
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CPU Common features library header file.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -855,7 +855,7 @@ FeatureControlGetConfigData (
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);
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/**
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Detects if Protected Processor Inventory Number feature supported on current
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Detects if Protected Processor Inventory Number feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@@ -889,14 +889,14 @@ PpinSupport (
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the Protected Processor Inventory
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@param[in] State If TRUE, then the Protected Processor Inventory
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Number feature must be enabled.
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If FALSE, then the Protected Processor Inventory
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If FALSE, then the Protected Processor Inventory
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Number feature must be disabled.
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@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
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@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
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initialized.
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@retval RETURN_DEVICE_ERROR Device can't change state because it has been
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@retval RETURN_DEVICE_ERROR Device can't change state because it has been
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locked.
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**/
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@@ -910,7 +910,7 @@ PpinInitialize (
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);
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/**
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Detects if Local machine check exception feature supported on current
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Detects if Local machine check exception feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@@ -4,7 +4,7 @@
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# This library registers CPU features defined in Intel(R) 64 and IA-32
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# Architectures Software Developer's Manual.
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#
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# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@@ -68,4 +68,4 @@
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gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
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@@ -235,7 +235,7 @@ McgCtlInitialize (
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}
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/**
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Detects if Local machine check exception feature supported on current
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Detects if Local machine check exception feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@@ -1,7 +1,7 @@
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/** @file
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Protected Processor Inventory Number(PPIN) feature.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -15,7 +15,7 @@
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#include "CpuCommonFeatures.h"
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/**
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Detects if Protected Processor Inventory Number feature supported on current
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Detects if Protected Processor Inventory Number feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@@ -41,13 +41,13 @@ PpinSupport (
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{
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MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
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if ((CpuInfo->DisplayFamily == 0x06) &&
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if ((CpuInfo->DisplayFamily == 0x06) &&
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((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
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(CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product
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(CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4
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(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
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(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
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(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
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(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
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)) {
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//
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// Check whether platform support this feature.
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@@ -69,14 +69,14 @@ PpinSupport (
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by CPU_FEATURE_GET_CONFIG_DATA. NULL if
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CPU_FEATURE_GET_CONFIG_DATA was not provided in
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RegisterCpuFeature().
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@param[in] State If TRUE, then the Protected Processor Inventory
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@param[in] State If TRUE, then the Protected Processor Inventory
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Number feature must be enabled.
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If FALSE, then the Protected Processor Inventory
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If FALSE, then the Protected Processor Inventory
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Number feature must be disabled.
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@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
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@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
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initialized.
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@retval RETURN_DEVICE_ERROR Device can't change state because it has been
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@retval RETURN_DEVICE_ERROR Device can't change state because it has been
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locked.
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**/
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@@ -1,7 +1,7 @@
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/** @file
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Intel Processor Trace feature.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -16,11 +16,11 @@
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///
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/// This macro define the max entries in the Topa table.
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/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
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/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
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/// current table (for circular array) or to the base of another table.
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/// At least 2 entries are needed because the list of entries must
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/// be terminated by an entry with the END bit set to 1, so 2
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/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
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/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
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/// current table (for circular array) or to the base of another table.
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/// At least 2 entries are needed because the list of entries must
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/// be terminated by an entry with the END bit set to 1, so 2
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/// entries are required to use a single valid entry.
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///
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#define MAX_TOPA_ENTRY_COUNT 2
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@@ -43,7 +43,7 @@ typedef struct {
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typedef struct {
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UINT32 NumberOfProcessors;
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UINT8 ProcTraceOutputScheme;
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UINT8 ProcTraceOutputScheme;
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UINT32 ProcTraceMemSize;
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UINTN *ThreadMemRegionTable;
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@@ -88,7 +88,7 @@ ProcTraceGetConfigData (
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}
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/**
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Detects if Intel Processor Trace feature supported on current
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Detects if Intel Processor Trace feature supported on current
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processor.
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@param[in] ProcessorNumber The index of the CPU executing this function.
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@@ -291,7 +291,7 @@ ProcTraceInitialize (
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//
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// Single Range output scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
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if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
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@@ -337,7 +337,7 @@ ProcTraceInitialize (
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//
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// ToPA(Table of physical address) scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
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if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
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//
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// Create ToPA structure aligned at 4KB for each logical thread
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