UefiCpuPkg: Clean up source files

1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:14:20 +08:00
parent 77695f4da3
commit 7367cc6c24
59 changed files with 614 additions and 614 deletions

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@@ -1,7 +1,7 @@
/** @file
CPU Common features library header file.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -855,7 +855,7 @@ FeatureControlGetConfigData (
);
/**
Detects if Protected Processor Inventory Number feature supported on current
Detects if Protected Processor Inventory Number feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -889,14 +889,14 @@ PpinSupport (
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@param[in] State If TRUE, then the Protected Processor Inventory
@param[in] State If TRUE, then the Protected Processor Inventory
Number feature must be enabled.
If FALSE, then the Protected Processor Inventory
If FALSE, then the Protected Processor Inventory
Number feature must be disabled.
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
initialized.
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
locked.
**/
@@ -910,7 +910,7 @@ PpinInitialize (
);
/**
Detects if Local machine check exception feature supported on current
Detects if Local machine check exception feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.

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@@ -4,7 +4,7 @@
# This library registers CPU features defined in Intel(R) 64 and IA-32
# Architectures Software Developer's Manual.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -68,4 +68,4 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES

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@@ -235,7 +235,7 @@ McgCtlInitialize (
}
/**
Detects if Local machine check exception feature supported on current
Detects if Local machine check exception feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.

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@@ -1,7 +1,7 @@
/** @file
Protected Processor Inventory Number(PPIN) feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,7 +15,7 @@
#include "CpuCommonFeatures.h"
/**
Detects if Protected Processor Inventory Number feature supported on current
Detects if Protected Processor Inventory Number feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -41,13 +41,13 @@ PpinSupport (
{
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
if ((CpuInfo->DisplayFamily == 0x06) &&
if ((CpuInfo->DisplayFamily == 0x06) &&
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
(CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product
(CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) {
//
// Check whether platform support this feature.
@@ -69,14 +69,14 @@ PpinSupport (
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@param[in] State If TRUE, then the Protected Processor Inventory
@param[in] State If TRUE, then the Protected Processor Inventory
Number feature must be enabled.
If FALSE, then the Protected Processor Inventory
If FALSE, then the Protected Processor Inventory
Number feature must be disabled.
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
@retval RETURN_SUCCESS Protected Processor Inventory Number feature is
initialized.
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
@retval RETURN_DEVICE_ERROR Device can't change state because it has been
locked.
**/

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@@ -1,7 +1,7 @@
/** @file
Intel Processor Trace feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,11 +16,11 @@
///
/// This macro define the max entries in the Topa table.
/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
/// current table (for circular array) or to the base of another table.
/// At least 2 entries are needed because the list of entries must
/// be terminated by an entry with the END bit set to 1, so 2
/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
/// current table (for circular array) or to the base of another table.
/// At least 2 entries are needed because the list of entries must
/// be terminated by an entry with the END bit set to 1, so 2
/// entries are required to use a single valid entry.
///
#define MAX_TOPA_ENTRY_COUNT 2
@@ -43,7 +43,7 @@ typedef struct {
typedef struct {
UINT32 NumberOfProcessors;
UINT8 ProcTraceOutputScheme;
UINT8 ProcTraceOutputScheme;
UINT32 ProcTraceMemSize;
UINTN *ThreadMemRegionTable;
@@ -88,7 +88,7 @@ ProcTraceGetConfigData (
}
/**
Detects if Intel Processor Trace feature supported on current
Detects if Intel Processor Trace feature supported on current
processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@@ -291,7 +291,7 @@ ProcTraceInitialize (
//
// Single Range output scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
@@ -337,7 +337,7 @@ ProcTraceInitialize (
//
// ToPA(Table of physical address) scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
//
// Create ToPA structure aligned at 4KB for each logical thread