ARM Packages: Use AND instead of BIC instruction with immediate

AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a
AND with the immediate inverted, but Clang's integrated assembler emits an
error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524

ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S

@@ -12,6 +12,7 @@
 //
 
 #include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
 
 #ifndef __clang__
 // Register definitions used by GCC for GICv3 access.
@@ -64,6 +65,6 @@ ASM_PFX(InitializeGicV3):
 
   // Remove the SCR.NS bit
   mrs     x0, scr_el3
-  bic     x0, x0, #1
+  and     x0, x0, #~SCR_NS
   msr     scr_el3, x0
   ret