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MdePkg/BaseLib: BaseLib for RISCV64 architecture

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Add RISC-V RV64 BaseLib functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
Abner Chang
2020-04-07 15:53:22 +08:00
committed by mergify[bot]
parent d3abb40d77
commit 7601b251fd
13 changed files with 374 additions and 1 deletions
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21
MdePkg/Library/BaseLib/RiscV64/FlushCache.S Normal file
View File

@@ -0,0 +1,21 @@
//------------------------------------------------------------------------------
//
// RISC-V cache operation.
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
.align 3
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
ASM_PFX(RiscVInvalidateInstCacheAsm):
fence.i
ret
ASM_PFX(RiscVInvalidateDataCacheAsm):
fence
ret