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UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

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Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
This commit is contained in:
Tuan Phan
2023-10-04 11:34:26 -07:00
committed by mergify[bot]
parent a445e1a42c
commit 772ec92577
3 changed files with 16 additions and 1 deletions
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6
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
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@@ -36,7 +36,7 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
STATIC UINTN mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
UINTN Index;
EFI_STATUS Status;
if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
return EFI_DEVICE_ERROR;
}
switch (SatpMode) {
case SATP_MODE_OFF:
return EFI_SUCCESS;