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UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

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Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
This commit is contained in:
Tuan Phan
2023-10-04 11:34:26 -07:00
committed by mergify[bot]
parent a445e1a42c
commit 772ec92577
3 changed files with 16 additions and 1 deletions
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8
UefiCpuPkg/UefiCpuPkg.dec
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@@ -396,6 +396,14 @@
# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
[PcdsFixedAtBuild.RISCV64]
## Indicate the maximum SATP mode allowed.
# 0 - Bare mode.
# 8 - 39bit mode.
# 9 - 48bit mode.
# 10 - 57bit mode.
gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.