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SourceLevelDebugPkg: Clean up source files

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:14:00 +08:00
parent ba0014b9f8
commit 77695f4da3
37 changed files with 272 additions and 272 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Common.c
View File

@@ -46,7 +46,7 @@ UINT16 mSerialNumberStrDesc[] = {
**/
VOID
XhcSetR32Bit(
IN OUT UINTN Register,
IN OUT UINTN Register,
IN UINT32 BitMask
)
{
@@ -65,7 +65,7 @@ XhcSetR32Bit(
**/
VOID
XhcClearR32Bit(
IN OUT UINTN Register,
IN OUT UINTN Register,
IN UINT32 BitMask
)
{
@@ -92,10 +92,10 @@ XhcWriteDebugReg (
)
{
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
DebugCapabilityBase = Handle->DebugCapabilityBase;
MmioWrite32 ((UINTN)(DebugCapabilityBase + Offset), Data);
return;
}
@@ -116,7 +116,7 @@ XhcReadDebugReg (
{
UINT32 Data;
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
DebugCapabilityBase = Handle->DebugCapabilityBase;
Data = MmioRead32 ((UINTN)(DebugCapabilityBase + Offset));
@@ -182,7 +182,7 @@ ProgramXhciBaseAddress (
UINT32 Low;
UINT32 High;
EFI_PHYSICAL_ADDRESS XhciMmioBase;
Low = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
High = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);
XhciMmioBase = (EFI_PHYSICAL_ADDRESS) (LShiftU64 ((UINT64) High, 32) | Low);
@@ -263,7 +263,7 @@ CalculateUsbDebugPortMmioBase (
VendorId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_VENDOR_ID_OFFSET);
DeviceId = PciRead16 (PcdGet32(PcdUsbXhciPciAddress) + PCI_DEVICE_ID_OFFSET);
if ((VendorId == 0xFFFF) || (DeviceId == 0xFFFF)) {
goto Done;
}
@@ -271,7 +271,7 @@ CalculateUsbDebugPortMmioBase (
ProgInterface = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET);
SubClassCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 1);
BaseCode = PciRead8 (PcdGet32(PcdUsbXhciPciAddress) + PCI_CLASSCODE_OFFSET + 2);
if ((ProgInterface != PCI_IF_XHCI) || (SubClassCode != PCI_CLASS_SERIAL_USB) || (BaseCode != PCI_CLASS_SERIAL)) {
goto Done;
}
@@ -282,7 +282,7 @@ CalculateUsbDebugPortMmioBase (
// Get capability pointer from HCCPARAMS at offset 0x10
//
CapabilityPointer = Handle->XhciMmioBase + (MmioRead32 ((UINTN)(Handle->XhciMmioBase + XHC_HCCPARAMS_OFFSET)) >> 16) * 4;
//
// Search XHCI debug capability
//
@@ -377,7 +377,7 @@ CreateEventRing (
EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
ASSERT (EventRing != NULL);
//
// Allocate Event Ring
//
@@ -390,7 +390,7 @@ CreateEventRing (
EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
EventRing->EventRingDequeue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) EventRing->EventRingSeg0;
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
// and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
@@ -473,7 +473,7 @@ CreateTransferRing (
{
VOID *Buf;
LINK_TRB *EndTrb;
Buf = AllocateAlignBuffer (sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0xF) == 0);
@@ -523,7 +523,7 @@ CreateDebugCapabilityContext (
UINT8 *ManufacturerStrDesc;
UINT8 *ProductStrDesc;
UINT8 *SerialNumberStrDesc;
//
// Allocate debug device context
//
@@ -531,10 +531,10 @@ CreateDebugCapabilityContext (
ASSERT (Buf != NULL);
ASSERT (((UINTN) Buf & 0xF) == 0);
ZeroMem (Buf, sizeof (XHC_DC_CONTEXT));
DebugCapabilityContext = (XHC_DC_CONTEXT *)(UINTN) Buf;
Handle->DebugCapabilityContext = (EFI_PHYSICAL_ADDRESS)(UINTN) DebugCapabilityContext;
//
// Initialize DbcInfoContext.
//
@@ -550,7 +550,7 @@ CreateDebugCapabilityContext (
DebugCapabilityContext->EpOutContext.EPType = ED_BULK_OUT;
DebugCapabilityContext->EpOutContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
DebugCapabilityContext->EpOutContext.AverageTRBLength = 0x1000;
//
// Initialize EpInContext.
//
@@ -558,7 +558,7 @@ CreateDebugCapabilityContext (
DebugCapabilityContext->EpInContext.EPType = ED_BULK_IN;
DebugCapabilityContext->EpInContext.MaxPacketSize = XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
DebugCapabilityContext->EpInContext.AverageTRBLength = 0x1000;
//
// Update string descriptor address
//
@@ -567,19 +567,19 @@ CreateDebugCapabilityContext (
ZeroMem (String0Desc, STRING0_DESC_LEN + MANU_DESC_LEN + PRODUCT_DESC_LEN + SERIAL_DESC_LEN);
CopyMem (String0Desc, mString0Desc, STRING0_DESC_LEN);
DebugCapabilityContext->DbcInfoContext.String0DescAddress = (UINT64)(UINTN)String0Desc;
ManufacturerStrDesc = String0Desc + STRING0_DESC_LEN;
CopyMem (ManufacturerStrDesc, mManufacturerStrDesc, MANU_DESC_LEN);
DebugCapabilityContext->DbcInfoContext.ManufacturerStrDescAddress = (UINT64)(UINTN)ManufacturerStrDesc;
ProductStrDesc = ManufacturerStrDesc + MANU_DESC_LEN;
CopyMem (ProductStrDesc, mProductStrDesc, PRODUCT_DESC_LEN);
DebugCapabilityContext->DbcInfoContext.ProductStrDescAddress = (UINT64)(UINTN)ProductStrDesc;
SerialNumberStrDesc = ProductStrDesc + PRODUCT_DESC_LEN;
CopyMem (SerialNumberStrDesc, mSerialNumberStrDesc, SERIAL_DESC_LEN);
DebugCapabilityContext->DbcInfoContext.SerialNumberStrDescAddress = (UINT64)(UINTN)SerialNumberStrDesc;
//
// Allocate and initialize the Transfer Ring for the Input Endpoint Context.
//
@@ -687,7 +687,7 @@ InitializeUsbDebugHardware (
return EFI_DEVICE_ERROR;
}
//
// If XHCI supports debug capability, hardware resource has been allocated,
// If XHCI supports debug capability, hardware resource has been allocated,
// but it has not been enabled, try to enable again.
//
goto Enable;
@@ -708,7 +708,7 @@ InitializeUsbDebugHardware (
//
// Reset port to get debug device discovered
//
//
for (Index = 0; Index < TotalUsb3Port; Index++) {
XhcSetR32Bit ((UINTN)XhciOpRegister + XHC_PORTSC_OFFSET + Index * 0x10, BIT4);
MicroSecondDelay (10 * 1000);
@@ -727,20 +727,20 @@ InitializeUsbDebugHardware (
Handle->UrbIn.Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer;
Handle->Data = (EFI_PHYSICAL_ADDRESS)(UINTN) Buffer + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE;
Handle->UrbOut.Data = Handle->UrbIn.Data + XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE * 2;
//
// Initialize event ring
//
ZeroMem (&Handle->EventRing, sizeof (EVENT_RING));
Status = CreateEventRing (Handle, &Handle->EventRing);
ASSERT_EFI_ERROR (Status);
//
// Init IN and OUT endpoint context
//
Status = CreateDebugCapabilityContext (Handle);
ASSERT_EFI_ERROR (Status);
//
// Init DCDDI1 and DCDDI2
//
@@ -748,7 +748,7 @@ InitializeUsbDebugHardware (
Handle,
XHC_DC_DCDDI1,
(UINT32)((XHCI_DEBUG_DEVICE_VENDOR_ID << 16) | XHCI_DEBUG_DEVICE_PROTOCOL)
);
);
XhcWriteDebugReg (
Handle,
@@ -759,7 +759,7 @@ InitializeUsbDebugHardware (
Enable:
if ((Handle->Initialized == USB3DBG_NOT_ENABLED) && (!Handle->ChangePortPower)) {
//
// If the first time detection is failed, turn port power off and on in order to
// If the first time detection is failed, turn port power off and on in order to
// reset port status this time, then try to check if debug device is ready again.
//
for (Index = 0; Index < TotalUsb3Port; Index++) {
@@ -775,9 +775,9 @@ Enable:
// Set DCE bit and LSE bit to "1" in DCCTRL in first initialization
//
XhcSetDebugRegBit (Handle, XHC_DC_DCCTRL, BIT1|BIT31);
XhcDetectDebugCapabilityReady (Handle);
Status = RETURN_SUCCESS;
if (!Handle->Ready) {
Handle->Initialized = USB3DBG_NOT_ENABLED;
@@ -823,7 +823,7 @@ DiscoverInitializeUsbDebugPort (
@param[in] Instance Debug port instance.
**/
**/
VOID
SetUsb3DebugPortInstance (
IN USB3_DEBUG_PORT_HANDLE *Instance
@@ -839,7 +839,7 @@ SetUsb3DebugPortInstance (
/**
Return USB3 debug instance address.
**/
**/
USB3_DEBUG_PORT_HANDLE *
GetUsb3DebugPortInstance (
VOID
@@ -1010,7 +1010,7 @@ DebugPortWriteBuffer (
XhcDataTransfer (UsbDebugPortHandle, EfiUsbDataOut, Buffer + Total, &Sent, DATA_TRANSFER_WRITE_TIMEOUT);
Total += Sent;
}
return Total;
}
@@ -1123,7 +1123,7 @@ DebugPortInitialize (
USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle;
//
// Validate the PCD PcdDebugPortHandleBufferSize value
// Validate the PCD PcdDebugPortHandleBufferSize value
//
ASSERT (PcdGet16 (PcdDebugPortHandleBufferSize) == sizeof (USB3_DEBUG_PORT_HANDLE));

10
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Dxe.c
View File

@@ -280,7 +280,7 @@ Usb3PciIoNotify (
);
if (!EFI_ERROR (Status) &&
(PciIoHandleBuffer != NULL) &&
(PciIoHandleCount != 0)) {
(PciIoHandleCount != 0)) {
for (Index = 0; Index < PciIoHandleCount; Index++) {
Status = gBS->HandleProtocol (
PciIoHandleBuffer[Index],
@@ -327,7 +327,7 @@ Usb3PciIoNotify (
/**
Return USB3 debug instance address pointer.
**/
**/
EFI_PHYSICAL_ADDRESS *
GetUsb3DebugPortInstanceAddrPtr (
VOID
@@ -391,7 +391,7 @@ Usb3AllocateDmaBuffer (
Allocate aligned memory for XHC's usage.
@param BufferSize The size, in bytes, of the Buffer.
@return A pointer to the allocated buffer or NULL if allocation fails.
**/
@@ -403,9 +403,9 @@ AllocateAlignBuffer (
EFI_PHYSICAL_ADDRESS TmpAddr;
EFI_STATUS Status;
VOID *Buf;
Buf = NULL;
if (gBS != NULL) {
if (mUsb3PciIo != NULL) {
Usb3AllocateDmaBuffer (

2
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Dxe.inf
View File

@@ -50,7 +50,7 @@
# The format of pci address please refer to SourceLevelDebugPkg.dec
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress ## CONSUMES
# Per XHCI spec, software shall impose a timeout between the detection of the Debug Host
# Per XHCI spec, software shall impose a timeout between the detection of the Debug Host
# connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout ## SOMETIMES_CONSUMES

46
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Internal.h
View File

@@ -248,12 +248,12 @@ typedef struct _ENDPOINT_CONTEXT_64 {
UINT32 RsvdZ5; // Reserved
UINT32 RsvdZ6;
UINT32 RsvdZ7;
UINT32 RsvdZ8;
UINT32 RsvdZ9;
UINT32 RsvdZ10;
UINT32 RsvdZ11;
UINT32 RsvdZ12;
UINT32 RsvdZ13;
UINT32 RsvdZ14;
@@ -396,7 +396,7 @@ typedef struct _DBC_INFO_CONTEXT {
UINT64 RsvdZ1:32;
UINT64 RsvdZ2;
UINT64 RsvdZ3;
UINT64 RsvdZ4;
UINT64 RsvdZ4;
} DBC_INFO_CONTEXT;
//
@@ -460,7 +460,7 @@ typedef struct _USB3_DEBUG_PORT_INSTANCE {
// The flag indicates debug capability is supported
//
BOOLEAN DebugSupport;
//
// The flag indicates debug device is ready
//
@@ -483,7 +483,7 @@ typedef struct _USB3_DEBUG_PORT_INSTANCE {
//
// The flag indicates if USB 3.0 ports has been turn off/on power
//
//
BOOLEAN ChangePortPower;
//
@@ -493,24 +493,24 @@ typedef struct _USB3_DEBUG_PORT_INSTANCE {
//
// XHCI OP RegisterBase address
//
//
EFI_PHYSICAL_ADDRESS XhciOpRegister;
//
// XHCI Debug Register Base Address
//
EFI_PHYSICAL_ADDRESS DebugCapabilityBase;
//
// XHCI Debug Capability offset
//
UINT64 DebugCapabilityOffset;
UINT64 DebugCapabilityOffset;
//
// XHCI Debug Context Address
//
EFI_PHYSICAL_ADDRESS DebugCapabilityContext;
//
// Transfer Ring
//
@@ -521,7 +521,7 @@ typedef struct _USB3_DEBUG_PORT_INSTANCE {
// EventRing
//
EVENT_RING EventRing;
//
// URB - Read
//
@@ -573,7 +573,7 @@ XhcSetDebugRegBit (
IN UINT32 Offset,
IN UINT32 Bit
);
/**
Write the data to the debug register.
@@ -581,7 +581,7 @@ XhcSetDebugRegBit (
@param Offset The offset of the debug register.
@param Data The data to write.
**/
**/
VOID
XhcWriteDebugReg (
IN USB3_DEBUG_PORT_HANDLE *Handle,
@@ -596,12 +596,12 @@ XhcWriteDebugReg (
@param[in] BitMask 32-bit mask
@return BOOLEAN - TRUE if all bits specified by the mask are enabled.
- FALSE even if one of the bits specified by the mask
- FALSE even if one of the bits specified by the mask
is not enabled.
**/
BOOLEAN
XhcIsBitSet(
UINTN Register,
UINTN Register,
UINT32 BitMask
);
@@ -613,7 +613,7 @@ XhcIsBitSet(
**/
VOID
XhcSetR32Bit(
UINTN Register,
UINTN Register,
UINT32 BitMask
);
@@ -625,13 +625,13 @@ XhcSetR32Bit(
**/
VOID
XhcClearR32Bit(
IN OUT UINTN Register,
IN OUT UINTN Register,
IN UINT32 BitMask
);
/**
Initialize USB3 debug port.
This method invokes various internal functions to facilitate
detection and initialization of USB3 debug port.
@@ -656,7 +656,7 @@ GetXhciPciCommand (
Allocate aligned memory for XHC's usage.
@param BufferSize The size, in bytes, of the Buffer.
@return A pointer to the allocated buffer or NULL if allocation fails.
**/
@@ -667,7 +667,7 @@ AllocateAlignBuffer (
/**
The real function to initialize USB3 debug port.
This method invokes various internal functions to facilitate
detection and initialization of USB3 debug port.
@@ -725,7 +725,7 @@ InitializeUsbDebugHardware (
/**
Return USB3 debug instance address pointer.
**/
**/
EFI_PHYSICAL_ADDRESS *
GetUsb3DebugPortInstanceAddrPtr (
VOID
@@ -734,7 +734,7 @@ GetUsb3DebugPortInstanceAddrPtr (
/**
Return USB3 debug instance address.
**/
**/
USB3_DEBUG_PORT_HANDLE *
GetUsb3DebugPortInstance (
VOID

4
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Pei.c
View File

@@ -179,7 +179,7 @@ Usb3GetIoMmu (
/**
Return USB3 debug instance address pointer.
**/
**/
EFI_PHYSICAL_ADDRESS *
GetUsb3DebugPortInstanceAddrPtr (
VOID
@@ -221,7 +221,7 @@ GetUsb3DebugPortInstanceAddrPtr (
Allocate aligned memory for XHC's usage.
@param BufferSize The size, in bytes, of the Buffer.
@return A pointer to the allocated buffer or NULL if allocation fails.
**/

2
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Pei.inf
View File

@@ -52,7 +52,7 @@
# The format of pci address please refer to SourceLevelDebugPkg.dec
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress ## CONSUMES
# Per XHCI spec, software shall impose a timeout between the detection of the Debug Host
# Per XHCI spec, software shall impose a timeout between the detection of the Debug Host
# connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout ## SOMETIMES_CONSUMES

46
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Transfer.c
View File

@@ -41,7 +41,7 @@ XhcSyncTrsRing (
TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
ASSERT (TrsTrb != NULL);
for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
@@ -185,9 +185,9 @@ IsTrbInTrsRing (
{
TRB_TEMPLATE *CheckedTrb;
UINTN Index;
CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
for (Index = 0; Index < Ring->TrbNumber; Index++) {
@@ -222,7 +222,7 @@ XhcCheckUrbResult (
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
ASSERT ((Handle != NULL) && (Urb != NULL));
if (Urb->Finished) {
@@ -230,12 +230,12 @@ XhcCheckUrbResult (
}
EvtTrb = NULL;
//
// Traverse the event ring to find out all new events from the previous check.
//
XhcSyncEventRing (Handle, &Handle->EventRing);
for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
@@ -245,13 +245,13 @@ XhcCheckUrbResult (
//
goto EXIT;
}
if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
continue;
}
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
CheckedUrb = Urb;
} else if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Handle->UrbIn.Ring), TRBPtr)) {
@@ -269,7 +269,7 @@ XhcCheckUrbResult (
} else {
continue;
}
if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
//
@@ -326,9 +326,9 @@ XhcRingDoorBell (
//
// 7.6.8.2 DCDB Register
//
//
Dcdb = (Urb->Direction == EfiUsbDataIn) ? 0x100 : 0x0;
XhcWriteDebugReg (
Handle,
XHC_DC_DCDB,
@@ -378,7 +378,7 @@ XhcExecTransfer (
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
}
}
//
// If URB transfer is error, restore transfer ring to original value before URB transfer
// This will make the current transfer TRB is always at the latest unused one in transfer ring.
@@ -425,7 +425,7 @@ XhcCreateTransferTrb (
} else {
EPRing = &Handle->TransferRingOut;
}
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
XhcSyncTrsRing (Handle, EPRing);
@@ -439,12 +439,12 @@ XhcCreateTransferTrb (
Trb->TrbNormal.ISP = 1;
Trb->TrbNormal.IOC = 1;
Trb->TrbNormal.Type = TRB_TYPE_NORMAL;
//
// Update the cycle bit to indicate this TRB has been consumed.
//
Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
return EFI_SUCCESS;
}
@@ -470,7 +470,7 @@ XhcCreateUrb (
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
if (Direction == EfiUsbDataIn) {
Urb = &Handle->UrbIn;
} else {
@@ -478,17 +478,17 @@ XhcCreateUrb (
}
UrbData = Urb->Data;
ZeroMem (Urb, sizeof (URB));
Urb->Direction = Direction;
//
// Allocate memory to move data from CAR or SMRAM to normal memory
// to make XHCI DMA successfully
// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
//
Urb->Data = UrbData;
if (Direction == EfiUsbDataIn) {
//
// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
@@ -502,7 +502,7 @@ XhcCreateUrb (
CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32) DataLen;
}
Status = XhcCreateTransferTrb (Handle, Urb);
ASSERT_EFI_ERROR (Status);
@@ -539,7 +539,7 @@ XhcDataTransfer (
{
URB *Urb;
EFI_STATUS Status;
//
// Validate the parameters
//
@@ -562,7 +562,7 @@ XhcDataTransfer (
if (Urb->Result == EFI_USB_NOERROR) {
Status = EFI_SUCCESS;
}
if (Direction == EfiUsbDataIn) {
//
// Move data from internal buffer to outside buffer (outside buffer may be in SMRAM...)