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SourceLevelDebugPkg: Clean up source files

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Liming Gao
2018-06-27 21:14:00 +08:00
parent ba0014b9f8
commit 77695f4da3
37 changed files with 272 additions and 272 deletions
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46
SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/DebugCommunicationLibUsb3Transfer.c
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@@ -41,7 +41,7 @@ XhcSyncTrsRing (
TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue;
ASSERT (TrsTrb != NULL);
for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
@@ -185,9 +185,9 @@ IsTrbInTrsRing (
{
TRB_TEMPLATE *CheckedTrb;
UINTN Index;
CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0;
ASSERT (Ring->TrbNumber == TR_RING_TRB_NUMBER);
for (Index = 0; Index < Ring->TrbNumber; Index++) {
@@ -222,7 +222,7 @@ XhcCheckUrbResult (
UINT64 XhcDequeue;
UINT32 High;
UINT32 Low;
ASSERT ((Handle != NULL) && (Urb != NULL));
if (Urb->Finished) {
@@ -230,12 +230,12 @@ XhcCheckUrbResult (
}
EvtTrb = NULL;
//
// Traverse the event ring to find out all new events from the previous check.
//
XhcSyncEventRing (Handle, &Handle->EventRing);
for (Index = 0; Index < Handle->EventRing.TrbNumber; Index++) {
Status = XhcCheckNewEvent (Handle, &Handle->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
@@ -245,13 +245,13 @@ XhcCheckUrbResult (
//
goto EXIT;
}
if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
continue;
}
TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Urb->Ring), TRBPtr)) {
CheckedUrb = Urb;
} else if (IsTrbInTrsRing ((TRANSFER_RING *)(UINTN)(Handle->UrbIn.Ring), TRBPtr)) {
@@ -269,7 +269,7 @@ XhcCheckUrbResult (
} else {
continue;
}
if ((EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) ||
(EvtTrb->Completecode == TRB_COMPLETION_SUCCESS)) {
//
@@ -326,9 +326,9 @@ XhcRingDoorBell (
//
// 7.6.8.2 DCDB Register
//
//
Dcdb = (Urb->Direction == EfiUsbDataIn) ? 0x100 : 0x0;
XhcWriteDebugReg (
Handle,
XHC_DC_DCDB,
@@ -378,7 +378,7 @@ XhcExecTransfer (
// If time out occurs.
//
Urb->Result |= EFI_USB_ERR_TIMEOUT;
}
}
//
// If URB transfer is error, restore transfer ring to original value before URB transfer
// This will make the current transfer TRB is always at the latest unused one in transfer ring.
@@ -425,7 +425,7 @@ XhcCreateTransferTrb (
} else {
EPRing = &Handle->TransferRingOut;
}
Urb->Ring = (EFI_PHYSICAL_ADDRESS)(UINTN) EPRing;
XhcSyncTrsRing (Handle, EPRing);
@@ -439,12 +439,12 @@ XhcCreateTransferTrb (
Trb->TrbNormal.ISP = 1;
Trb->TrbNormal.IOC = 1;
Trb->TrbNormal.Type = TRB_TYPE_NORMAL;
//
// Update the cycle bit to indicate this TRB has been consumed.
//
Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
return EFI_SUCCESS;
}
@@ -470,7 +470,7 @@ XhcCreateUrb (
EFI_STATUS Status;
URB *Urb;
EFI_PHYSICAL_ADDRESS UrbData;
if (Direction == EfiUsbDataIn) {
Urb = &Handle->UrbIn;
} else {
@@ -478,17 +478,17 @@ XhcCreateUrb (
}
UrbData = Urb->Data;
ZeroMem (Urb, sizeof (URB));
Urb->Direction = Direction;
//
// Allocate memory to move data from CAR or SMRAM to normal memory
// to make XHCI DMA successfully
// re-use the pre-allocate buffer in PEI to avoid DXE memory service or gBS are not ready
//
Urb->Data = UrbData;
if (Direction == EfiUsbDataIn) {
//
// Do not break URB data in buffer as it may contain the data which were just put in via DMA by XHC
@@ -502,7 +502,7 @@ XhcCreateUrb (
CopyMem ((VOID*)(UINTN) Urb->Data, Data, DataLen);
Urb->DataLen = (UINT32) DataLen;
}
Status = XhcCreateTransferTrb (Handle, Urb);
ASSERT_EFI_ERROR (Status);
@@ -539,7 +539,7 @@ XhcDataTransfer (
{
URB *Urb;
EFI_STATUS Status;
//
// Validate the parameters
//
@@ -562,7 +562,7 @@ XhcDataTransfer (
if (Urb->Result == EFI_USB_NOERROR) {
Status = EFI_SUCCESS;
}
if (Direction == EfiUsbDataIn) {
//
// Move data from internal buffer to outside buffer (outside buffer may be in SMRAM...)