From 77d172b76d4c14a667a85014563cc41d254044a4 Mon Sep 17 00:00:00 2001 From: Jeremy Linton Date: Thu, 14 Jul 2016 08:58:30 -0500 Subject: [PATCH] ArmPlatformPkg/ArmJuno: Correct AXI->PCIe translation comments The AXI<->PCIe translation comments are out of date with respect to the code. In the first case the AXI master port is incorrectly called a slave. In the second case the the translation direction indicated for the slave port is the wrong direction. Correct both of these comments to reflect what the code is doing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton Reviewed-by: Leif Lindholm --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index d549903309..57e9e9df54 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -84,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -101,7 +101,7 @@ HWPciRbInit ( ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // AXI4 Slave 1 -> PCIE Window 0 Address Translations // TranslationTable = VEXPRESS_ATR_AXI4_SLV1;